arm:lpc32xx:Fix I2C communication to ISP1301

When transmitting a byte via I2C? bits 8 and 9 issue start and stop
conditions respectively. The function that writes to configuration
registers in the ISP1301 OTG PHY doesn't mask off invalid data bits
(bits 8 through 31) so start/stop conditions are being mistakenly
issued. Although the ISP1301 seemingly tolerated this behavior the
"functionally equivalent" STOTG04E did not.

The fix is simply to mask off the invalid data from register and
data values

Signed-off-by: Bangaragiri G <bangaragiri.g@nxp.com>

diff --git a/board/nxp/ea3250/ea3250.c b/board/nxp/ea3250/ea3250.c
index 3ba7970..3d1f025 100644 (file)
--- a/board/nxp/ea3250/ea3250.c
+++ b/board/nxp/ea3250/ea3250.c
@@ -227,7 +227,7 @@ static int isp1301_get_value(int reg)
        OTG->otg_i2c.otg_i2c_txrx = ((ISP1301_I2C_ADDR << 1) | I2C_START_BIT);
 
        /* register (offset) to read from */
-       OTG->otg_i2c.otg_i2c_txrx = reg;
+       OTG->otg_i2c.otg_i2c_txrx = (reg & 0xff);
 
        /* repeat start */
        OTG->otg_i2c.otg_i2c_txrx = ((ISP1301_I2C_ADDR << 1) | I2C_START_BIT | I2C_READ);
@@ -254,9 +254,9 @@ static int isp1301_set_value(int reg, int value)
        OTG->otg_i2c.otg_i2c_txrx = ((ISP1301_I2C_ADDR << 1) | I2C_START_BIT);
 
        /* offset to write to */
-       OTG->otg_i2c.otg_i2c_txrx = (reg | I2C_WRITE);
+       OTG->otg_i2c.otg_i2c_txrx = ((reg & 0xff) | I2C_WRITE);
        /* value to write */
-       OTG->otg_i2c.otg_i2c_txrx = (value | I2C_STOP_BIT);
+       OTG->otg_i2c.otg_i2c_txrx = ((value & 0xff) | I2C_STOP_BIT);
 
        /* wait for transmit done (TDI) */
        while (((OTG->otg_i2c.otg_i2c_stat & I2C_TDI) != I2C_TDI) && n++ < 100000);