serial: lpc32xx: Move HSU_OFFSET to platform code
authorBangaragiri G <bangaragiri.g@nxp.com>
Wed, 20 Apr 2011 04:15:21 +0000 (09:15 +0530)
committerBangaragiri G <bangaragiri.g@nxp.com>
Wed, 20 Apr 2011 04:15:21 +0000 (09:15 +0530)
The First bit sampling value for HSUART value is moved
to platform serial code. The user can set this as per transceivers
on the board & baud rate used

Signed-off-by: Bangaragiri G <bangaragiri.g@nxp.com>

arch/arm/mach-lpc32xx/include/mach/board.h
arch/arm/mach-lpc32xx/serial.c
drivers/serial/lpc32xx_hs.c

index c8df348..3049eaf 100644 (file)
@@ -22,6 +22,7 @@
 
 #include "platform.h"
 #include <linux/mtd/partitions.h>
+#include <linux/serial_core.h>
 
 /*
  * NAND platform configuration structure
@@ -73,6 +74,13 @@ struct lpc32xx_usbd_cfg
         usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
 };
 
+/*
+ * High Speed UART configuration structure
+ */
+struct lpc32xx_hsuart_port {
+       struct uart_port port;
+       unsigned int fbit_sam;
+};
 
 #endif /* __ASM_ARCH_BOARD_H */
 
index 78763ec..7b3fc03 100644 (file)
@@ -27,6 +27,7 @@
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
+#include <mach/board.h>
 #include "common.h"
 
 #define LPC32XX_SUART_FIFO_SIZE        64
@@ -140,35 +141,44 @@ static struct platform_device serial_std_platform_device = {
 };
 
 /* High speed serial ports */
-static struct uart_port serial_hspd_platform_data[] = {
+static struct lpc32xx_hsuart_port serial_hspd_platform_data[] = {
 #ifdef CONFIG_ARCH_LPC32XX_HSUART1_SELECT
        {
-               .membase        = io_p2v(LPC32XX_HS_UART1_BASE),
-               .mapbase        = LPC32XX_HS_UART1_BASE,
-               .irq            = IRQ_LPC32XX_UART_IIR1,
-               .regshift       = 2,
-               .iotype         = UPIO_MEM32,
-               .flags          = UPF_BOOT_AUTOCONF,
+               .port                                   = {
+                       .membase        = io_p2v(LPC32XX_HS_UART1_BASE),
+                       .mapbase        = LPC32XX_HS_UART1_BASE,
+                       .irq            = IRQ_LPC32XX_UART_IIR1,
+                       .regshift       = 2,
+                       .iotype         = UPIO_MEM32,
+                       .flags          = UPF_BOOT_AUTOCONF,
+               },
+               .fbit_sam       = 20,
        },
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_HSUART2_SELECT
        {
-               .membase        = io_p2v(LPC32XX_HS_UART2_BASE),
-               .mapbase        = LPC32XX_HS_UART2_BASE,
-               .irq            = IRQ_LPC32XX_UART_IIR2,
-               .regshift       = 2,
-               .iotype         = UPIO_MEM32,
-               .flags          = UPF_BOOT_AUTOCONF,
+               .port                                   = {
+                       .membase        = io_p2v(LPC32XX_HS_UART2_BASE),
+                       .mapbase        = LPC32XX_HS_UART2_BASE,
+                       .irq            = IRQ_LPC32XX_UART_IIR2,
+                       .regshift       = 2,
+                       .iotype         = UPIO_MEM32,
+                       .flags          = UPF_BOOT_AUTOCONF,
+               },
+               .fbit_sam       = 20,
        },
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_HSUART7_SELECT
        {
-               .membase        = io_p2v(LPC32XX_HS_UART7_BASE),
-               .mapbase        = LPC32XX_HS_UART7_BASE,
-               .irq            = IRQ_LPC32XX_UART_IIR7,
-               .regshift       = 2,
-               .iotype         = UPIO_MEM32,
-               .flags          = UPF_BOOT_AUTOCONF,
+               .port                                   = {
+                       .membase        = io_p2v(LPC32XX_HS_UART7_BASE),
+                       .mapbase        = LPC32XX_HS_UART7_BASE,
+                       .irq            = IRQ_LPC32XX_UART_IIR7,
+                       .regshift       = 2,
+                       .iotype         = UPIO_MEM32,
+                       .flags          = UPF_BOOT_AUTOCONF,
+               },
+               .fbit_sam       = 20,
        },
 #endif
        { },
@@ -269,8 +279,8 @@ void __init lpc32xx_serial_init(void)
 
         /* Setup of HSUART devices */
         for (i = 0; i < ARRAY_SIZE(serial_hspd_platform_data) - 1; i++) {
-                serial_hspd_platform_data[i].line = i;
-                serial_hspd_platform_data[i].uartclk = tmpclk;
+                serial_hspd_platform_data[i].port.line = i;
+                serial_hspd_platform_data[i].port.uartclk = tmpclk;
        }
 
        /* Disable UART5->USB transparent mode or USB won't work */
index f66ec1e..e1bcf2d 100644 (file)
@@ -31,6 +31,8 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
+#include <mach/board.h>
+
 /*
  * High speed UART register offsets
  */
 
 #define MODNAME "lpc32xx_hsuart"
 
-struct lpc32xx_hsuart_port {
-       struct uart_port port;
-};
-
 #define FIFO_READ_LIMIT 128
 #define MAX_PORTS 3
 #define LPC32XX_TTY_NAME "ttyTX"
@@ -456,6 +454,7 @@ static int serial_lpc32xx_startup(struct uart_port *port)
        int retval;
        unsigned long flags;
        u32 tmp;
+       struct lpc32xx_hsuart_port *p = (struct lpc32xx_hsuart_port *)port;
 
        spin_lock_irqsave(&port->lock, flags);
 
@@ -472,7 +471,7 @@ static int serial_lpc32xx_startup(struct uart_port *port)
         * and default FIFO trigger levels
         */
        tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
-               LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
+               LPC32XX_HSU_OFFSET(p->fbit_sam) | LPC32XX_HSU_TMO_INACT_4B;
        __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 
        spin_unlock_irqrestore(&port->lock, flags);
@@ -491,11 +490,12 @@ static void serial_lpc32xx_shutdown(struct uart_port *port)
 {
        u32 tmp;
        unsigned long flags;
+       struct lpc32xx_hsuart_port *p = (struct lpc32xx_hsuart_port *)port;
 
        spin_lock_irqsave(&port->lock, flags);
 
        tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
-               LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
+               LPC32XX_HSU_OFFSET(p->fbit_sam) | LPC32XX_HSU_TMO_INACT_4B;
        __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 
        spin_unlock_irqrestore(&port->lock, flags);
@@ -579,6 +579,7 @@ static int serial_lpc32xx_request_port(struct uart_port *port)
 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
 {
        int ret;
+       struct lpc32xx_hsuart_port *p = (struct lpc32xx_hsuart_port *)port;
 
        ret = serial_lpc32xx_request_port(port);
        if (ret < 0)
@@ -597,7 +598,7 @@ static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
        /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
           and default FIFO trigger levels */
        __raw_writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
-               LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
+               LPC32XX_HSU_OFFSET(p->fbit_sam) | LPC32XX_HSU_TMO_INACT_4B,
                LPC32XX_HSUART_CTRL(port->membase));
 }
 
@@ -636,25 +637,34 @@ static struct uart_ops serial_lpc32xx_pops = {
  */
 static int __devinit serial_hs_lpc32xx_probe(struct platform_device *pdev)
 {
-       struct uart_port *p = pdev->dev.platform_data;
+       struct lpc32xx_hsuart_port *p = pdev->dev.platform_data;
        struct lpc32xx_hsuart_port *pdr;
        int i, ret = 0;
 
        uarts_registered = 0;
-       for (i = 0; p && (p->flags != 0); i++) {
+       for (i = 0; p && (p->port.flags != 0); i++) {
                pdr = &lpc32xx_hs_ports[i];
                memset(pdr, 0, sizeof(struct lpc32xx_hsuart_port));
 
-               pdr->port.iotype        = p->iotype;
-               pdr->port.membase       = p->membase;
-               pdr->port.mapbase       = p->mapbase;
-               pdr->port.irq           = p->irq;
-               pdr->port.uartclk       = p->uartclk;
-               pdr->port.regshift      = p->regshift;
-               pdr->port.flags         = p->flags | UPF_FIXED_PORT;
+               pdr->port.iotype        = p->port.iotype;
+               pdr->port.membase       = p->port.membase;
+               pdr->port.mapbase       = p->port.mapbase;
+               pdr->port.irq           = p->port.irq;
+               pdr->port.uartclk       = p->port.uartclk;
+               pdr->port.regshift      = p->port.regshift;
+               pdr->port.flags         = p->port.flags | UPF_FIXED_PORT;
                pdr->port.dev           = &pdev->dev;
                pdr->port.ops           = &serial_lpc32xx_pops;
-               pdr->port.line          = p->line;
+               pdr->port.line          = p->port.line;
+               pdr->fbit_sam           = p->fbit_sam;
+
+               /* If First sample point is beyond limit,
+                * set it to default value - 20
+                */
+               if((pdr->fbit_sam < 0) || (pdr->fbit_sam > 31)) {
+                       pdr->fbit_sam = 20;
+               }
+
                spin_lock_init(&pdr->port.lock);
 
                uart_add_one_port(&lpc32xx_hs_reg, &pdr->port);