arm:lpc32xx:fdi3250 - config with mmc, no frame buffer
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / fdi3250.c
index c4073bb..55ca1ff 100644 (file)
@@ -103,18 +103,12 @@ static void fdi3250_spi_cs_set(u32 control)
 
 /* SPIDEV parameters */
 static struct pl022_config_chip spi0_chip_info = {
-       .lbm                    = LOOPBACK_DISABLED,
        .com_mode               = INTERRUPT_TRANSFER,
        .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
        .hierarchy              = SSP_MASTER,
        .slave_tx_disable       = 0,
-       .endian_tx              = SSP_TX_LSB,
-       .endian_rx              = SSP_RX_LSB,
-       .data_size              = SSP_DATA_BITS_8,
        .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
        .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
-       .clk_phase              = SSP_CLK_FIRST_EDGE,
-       .clk_pol                = SSP_CLK_POL_IDLE_LOW,
        .ctrl_len               = SSP_BITS_8,
        .wait_state             = SSP_MWIRE_WAIT_ZERO,
        .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -284,12 +278,56 @@ struct amba_device lpc32xx_clcd_device = {
 };
 #endif
 
+#if defined (CONFIG_MMC_ARMMMCI)
+static u32 mmc_translate_vdd(struct device *dev, unsigned int vdd)
+{
+       return 0;
+}
+
+unsigned int fdi_mmc_status_always_on(struct device *dev)
+{
+       return 0;
+}
+/*
+ * Board specific MMC driver data
+ */
+struct mmci_platform_data lpc32xx_plat_data = {
+       .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
+       .translate_vdd  = mmc_translate_vdd,
+       .capabilities   = MMC_CAP_4_BIT_DATA,
+       .gpio_wp        = ARCH_NR_GPIOS + 1,
+       .gpio_cd        = ARCH_NR_GPIOS + 1,
+       .status         = fdi_mmc_status_always_on,
+};
+
+/*
+ * SD card controller resources
+ */
+struct amba_device lpc32xx_mmc_device = {
+       .dev = {
+               .coherent_dma_mask      = ~0,
+               .init_name                 = "dev:mmc0",
+               .platform_data          = &lpc32xx_plat_data,
+       },
+       .res = {
+               .start                  = LPC32XX_SD_BASE,
+               .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
+               .flags                  = IORESOURCE_MEM,
+       },
+       .dma_mask                       = ~0,
+       .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
+};
+#endif
+
 /* AMBA based devices list */
 static struct amba_device *amba_devs[] __initdata = {
        &lpc32xx_ssp0_device,
 #if defined (CONFIG_FB_ARMCLCD)
        &lpc32xx_clcd_device,
 #endif
+#if defined(CONFIG_MMC_ARMMMCI)
+       &lpc32xx_mmc_device,
+#endif
 };
 
 /*
@@ -362,7 +400,8 @@ struct lpc32XX_nand_cfg lpc32xx_nandcfg =
         .rwidth                 = 34666666,
         .rhold                  = 104000000,
         .rsetup                 = 200000000,
-        .use16bus               = 0,
+       .use_bbt                = true,
+       .polled_completion      = false,
         .enable_write_prot      = nandwp_enable,
         .partition_info         = fdi3250_nand_partitions,
 };