serial: lpc32xx: Move HSU_OFFSET to platform code
[linux-2.6.34-lpc32xx.git] / drivers / serial / lpc32xx_hs.c
1 /*
2  * drivers/serial/lpc32xx_hs.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial.h>
28 #include <linux/platform_device.h>
29 #include <linux/delay.h>
30 #include <linux/nmi.h>
31 #include <linux/io.h>
32 #include <linux/irq.h>
33
34 #include <mach/board.h>
35
36 /*
37  * High speed UART register offsets
38  */
39 #define LPC32XX_HSUART_FIFO(x)                  (x + 0x00)
40 #define LPC32XX_HSUART_LEVEL(x)                 (x + 0x04)
41 #define LPC32XX_HSUART_IIR(x)                   (x + 0x08)
42 #define LPC32XX_HSUART_CTRL(x)                  (x + 0x0C)
43 #define LPC32XX_HSUART_RATE(x)                  (x + 0x10)
44
45 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
46 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
47 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
48
49 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
50 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
51
52 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
53 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
54 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
55 #define LPC32XX_HSU_FE_INT                      (1 << 3)
56 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
57 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
58 #define LPC32XX_HSU_TX_INT                      (1 << 0)
59
60 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
61 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
62 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
63 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
64 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
65 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
66 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
67 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
68 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
69 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
70 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
71 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
72 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
73 #define LPC32XX_HSU_BREAK                       (1 << 8)
74 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
75 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
76 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
77 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
78 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
79 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
80 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
81 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
82 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
83 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
84 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
85 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
86 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
87 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
88
89 #define MODNAME "lpc32xx_hsuart"
90
91 #define FIFO_READ_LIMIT 128
92 #define MAX_PORTS 3
93 #define LPC32XX_TTY_NAME "ttyTX"
94 #define LPC32XX_TTY_MINOR_START 196
95 #define LPC32XX_TTY_MAJOR 204
96 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
97
98 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
99 static void wait_for_xmit_empty(struct uart_port *port)
100 {
101         unsigned int timeout = 10000;
102
103         do {
104                 if (LPC32XX_HSU_TX_LEV(__raw_readl(LPC32XX_HSUART_LEVEL(
105                         port->membase))) == 0)
106                         break;
107                 if (--timeout == 0)
108                         break;
109                 udelay(1);
110         } while (1);
111 }
112
113 static void wait_for_xmit_ready(struct uart_port *port)
114 {
115         unsigned int timeout = 10000;
116
117         while (1) {
118                 if (LPC32XX_HSU_TX_LEV(__raw_readl(LPC32XX_HSUART_LEVEL(
119                         port->membase))) < 32)
120                         break;
121                 if (--timeout == 0)
122                         break;
123                 udelay(1);
124         }
125 }
126
127 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
128 {
129         wait_for_xmit_ready(port);
130         __raw_writel((u32) ch, LPC32XX_HSUART_FIFO(port->membase));
131 }
132
133 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
134         unsigned int count) {
135         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
136         unsigned long flags;
137         int locked = 1;
138
139         touch_nmi_watchdog();
140         local_irq_save(flags);
141         if (up->port.sysrq)
142                 locked = 0;
143         else if (oops_in_progress)
144                 locked = spin_trylock(&up->port.lock);
145         else
146                 spin_lock(&up->port.lock);
147
148         uart_console_write(&up->port, s, count,
149                 lpc32xx_hsuart_console_putchar);
150         wait_for_xmit_empty(&up->port);
151
152         if (locked)
153                 spin_unlock(&up->port.lock);
154         local_irq_restore(flags);
155 }
156
157 static int __init lpc32xx_hsuart_console_setup(struct console *co,
158         char *options) {
159         struct uart_port *port;
160         int baud = 115200;
161         int bits = 8;
162         int parity = 'n';
163         int flow = 'n';
164
165         if (co->index >= MAX_PORTS)
166                 co->index = 0;
167
168         port = &lpc32xx_hs_ports[co->index].port;
169         if (!port->membase)
170                 return -ENODEV;
171
172         if (options)
173                 uart_parse_options(options, &baud, &parity, &bits, &flow);
174
175         return uart_set_options(port, co, baud, parity, bits, flow);
176 }
177
178 static struct uart_driver lpc32xx_hs_reg;
179 static struct console lpc32xx_hsuart_console = {
180         .name           = LPC32XX_TTY_NAME,
181         .write          = lpc32xx_hsuart_console_write,
182         .device         = uart_console_device,
183         .setup          = lpc32xx_hsuart_console_setup,
184         .flags          = CON_PRINTBUFFER,
185         .index          = -1,
186         .data           = &lpc32xx_hs_reg,
187 };
188
189 static int __init lpc32xx_hsuart_console_init(void)
190 {
191         register_console(&lpc32xx_hsuart_console);
192         return 0;
193 }
194 console_initcall(lpc32xx_hsuart_console_init);
195
196 #define LPC32XX_HSUART_CONSOLE  (&lpc32xx_hsuart_console)
197 #else
198 #define LPC32XX_HSUART_CONSOLE NULL
199 #endif
200
201 static struct uart_driver lpc32xx_hs_reg = {
202         .owner          = THIS_MODULE,
203         .driver_name    = MODNAME,
204         .dev_name       = LPC32XX_TTY_NAME,
205         .major          = LPC32XX_TTY_MAJOR,
206         .minor          = LPC32XX_TTY_MINOR_START,
207         .nr             = MAX_PORTS,
208         .cons           = LPC32XX_HSUART_CONSOLE,
209 };
210 static int uarts_registered;
211
212 static unsigned int __serial_get_clock_div(unsigned long uartclk,
213         unsigned long rate) {
214         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
215         u32 rate_diff;
216
217         /* Find the closest divider to get the desired clock rate */
218         div = uartclk / rate;
219         goodrate = hsu_rate = (div / 14) - 1;
220         if (hsu_rate != 0)
221                 hsu_rate--;
222
223         /* Tweak divider */
224         l_hsu_rate = hsu_rate + 3;
225         rate_diff = 0xFFFFFFFF;
226
227         while (hsu_rate < l_hsu_rate) {
228                 comprate = uartclk / ((hsu_rate + 1) * 14);
229                 if (abs(comprate - rate) < rate_diff) {
230                         goodrate = hsu_rate;
231                         rate_diff = abs(comprate - rate);
232                 }
233
234                 hsu_rate++;
235         }
236         if (hsu_rate > 0xFF)
237                 hsu_rate = 0xFF;
238
239         return goodrate;
240 }
241
242 static void __serial_uart_flush(struct uart_port *port)
243 {
244         u32 tmp;
245         int cnt = 0;
246
247         while ((__raw_readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
248                 (cnt++ < FIFO_READ_LIMIT))
249                 tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
250 }
251
252 static void __serial_lpc32xx_rx(struct uart_port *port)
253 {
254         unsigned int tmp, flag;
255
256         /* Read data from FIFO and push into terminal */
257         tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
258         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
259                 flag = TTY_NORMAL;
260                 port->icount.rx++;
261
262                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
263                         /* Framing error */
264                         __raw_writel(LPC32XX_HSU_FE_INT,
265                                 LPC32XX_HSUART_IIR(port->membase));
266                         port->icount.frame++;
267                         flag = TTY_FRAME;
268                         tty_insert_flip_char(port->state->port.tty, 0,
269                                 TTY_FRAME);
270                         tty_schedule_flip(port->state->port.tty);
271                 }
272
273                 tty_insert_flip_char(port->state->port.tty, (tmp & 0xFF),
274                         flag);
275
276                 tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
277         }
278 }
279
280 static void __serial_lpc32xx_tx(struct uart_port *port)
281 {
282         struct circ_buf *xmit = &port->state->xmit;
283         unsigned int tmp;
284
285         if (port->x_char) {
286                 __raw_writel((u32) port->x_char,
287                         LPC32XX_HSUART_FIFO(port->membase));
288                 port->icount.tx++;
289                 port->x_char = 0;
290                 return;
291         }
292
293         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
294                 goto exit_tx;
295
296         /* Transfer data */
297         while (LPC32XX_HSU_TX_LEV(__raw_readl(
298                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
299                 __raw_writel((u32) xmit->buf[xmit->tail],
300                         LPC32XX_HSUART_FIFO(port->membase));
301                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
302                 port->icount.tx++;
303                 if (uart_circ_empty(xmit))
304                         break;
305         }
306
307         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
308                 uart_write_wakeup(port);
309
310 exit_tx:
311         if (uart_circ_empty(xmit)) {
312                 tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
313                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
314                 __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
315         }
316 }
317
318 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
319 {
320         struct uart_port *port = dev_id;
321         u32 status;
322
323         spin_lock(&port->lock);
324
325         /* Read UART status and clear latched interrupts */
326         status = __raw_readl(LPC32XX_HSUART_IIR(port->membase));
327
328         if (status & LPC32XX_HSU_BRK_INT) {
329                 /* Break received */
330                 __raw_writel(LPC32XX_HSU_BRK_INT,
331                         LPC32XX_HSUART_IIR(port->membase));
332                 port->icount.brk++;
333                 uart_handle_break(port);
334         }
335
336         /* Framing error */
337         if (status & LPC32XX_HSU_FE_INT)
338                 __raw_writel(LPC32XX_HSU_FE_INT,
339                         LPC32XX_HSUART_IIR(port->membase));
340
341         if (status & LPC32XX_HSU_RX_OE_INT) {
342                 /* Receive FIFO overrun */
343                 __raw_writel(LPC32XX_HSU_RX_OE_INT,
344                         LPC32XX_HSUART_IIR(port->membase));
345                 port->icount.overrun++;
346                 tty_insert_flip_char(port->state->port.tty, 0, TTY_OVERRUN);
347                 tty_schedule_flip(port->state->port.tty);
348         }
349
350         /* Data received? */
351         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
352                 __serial_lpc32xx_rx(port);
353                 spin_unlock(&port->lock);
354                 tty_flip_buffer_push(port->state->port.tty);
355                 spin_lock(&port->lock);
356         }
357
358         /* Transmit data request? */
359         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
360                 __raw_writel(LPC32XX_HSU_TX_INT,
361                         LPC32XX_HSUART_IIR(port->membase));
362                 __serial_lpc32xx_tx(port);
363         }
364
365         spin_unlock(&port->lock);
366
367         return IRQ_HANDLED;
368 }
369
370 /* port->lock is not held.  */
371 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
372 {
373         unsigned int ret = 0;
374
375         if (LPC32XX_HSU_TX_LEV(__raw_readl(
376                 LPC32XX_HSUART_LEVEL(port->membase))) == 0)
377                 ret = TIOCSER_TEMT;
378
379         return ret;
380 }
381
382 /* port->lock held by caller.  */
383 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
384         unsigned int mctrl) {
385         /* No signals are supported on HS UARTs */
386 }
387
388 /* port->lock is held by caller and interrupts are disabled.  */
389 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
390 {
391         /* No signals are supported on HS UARTs */
392         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
393 }
394
395 /* port->lock held by caller.  */
396 static void serial_lpc32xx_stop_tx(struct uart_port *port)
397 {
398         u32 tmp;
399
400         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
401         tmp &= ~LPC32XX_HSU_TX_INT_EN;
402         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
403 }
404
405 /* port->lock held by caller.  */
406 static void serial_lpc32xx_start_tx(struct uart_port *port)
407 {
408         u32 tmp;
409
410         __serial_lpc32xx_tx(port);
411         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
412         tmp |= LPC32XX_HSU_TX_INT_EN;
413         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
414 }
415
416 /* port->lock held by caller.  */
417 static void serial_lpc32xx_stop_rx(struct uart_port *port)
418 {
419         u32 tmp;
420
421         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
422         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
423         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
424
425         __raw_writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
426                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
427 }
428
429 /* port->lock held by caller.  */
430 static void serial_lpc32xx_enable_ms(struct uart_port *port)
431 {
432         /* Modem status is not supported */
433 }
434
435 /* port->lock is not held.  */
436 static void serial_lpc32xx_break_ctl(struct uart_port *port,
437         int break_state) {
438         unsigned long flags;
439         u32 tmp;
440
441         spin_lock_irqsave(&port->lock, flags);
442         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
443         if (break_state != 0)
444                 tmp |= LPC32XX_HSU_BREAK;
445         else
446                 tmp &= ~LPC32XX_HSU_BREAK;
447         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
448         spin_unlock_irqrestore(&port->lock, flags);
449 }
450
451 /* port->lock is not held.  */
452 static int serial_lpc32xx_startup(struct uart_port *port)
453 {
454         int retval;
455         unsigned long flags;
456         u32 tmp;
457         struct lpc32xx_hsuart_port *p = (struct lpc32xx_hsuart_port *)port;
458
459         spin_lock_irqsave(&port->lock, flags);
460
461         __serial_uart_flush(port);
462
463         __raw_writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
464                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
465                 LPC32XX_HSUART_IIR(port->membase));
466
467         __raw_writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
468
469         /*
470          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
471          * and default FIFO trigger levels
472          */
473         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
474                 LPC32XX_HSU_OFFSET(p->fbit_sam) | LPC32XX_HSU_TMO_INACT_4B;
475         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
476
477         spin_unlock_irqrestore(&port->lock, flags);
478
479         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
480                              0, MODNAME, port);
481         if (!retval)
482                 __raw_writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
483                         LPC32XX_HSUART_CTRL(port->membase));
484
485         return retval;
486 }
487
488 /* port->lock is not held.  */
489 static void serial_lpc32xx_shutdown(struct uart_port *port)
490 {
491         u32 tmp;
492         unsigned long flags;
493         struct lpc32xx_hsuart_port *p = (struct lpc32xx_hsuart_port *)port;
494
495         spin_lock_irqsave(&port->lock, flags);
496
497         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
498                 LPC32XX_HSU_OFFSET(p->fbit_sam) | LPC32XX_HSU_TMO_INACT_4B;
499         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
500
501         spin_unlock_irqrestore(&port->lock, flags);
502
503         free_irq(port->irq, port);
504 }
505
506 /* port->lock is not held.  */
507 static void serial_lpc32xx_set_termios(struct uart_port *port,
508         struct ktermios *termios, struct ktermios *old)
509 {
510         unsigned long flags;
511         unsigned int baud, quot;
512         u32 tmp;
513
514         /* Always 8-bit, no parity, 1 stop bit */
515         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
516         termios->c_cflag |= CS8;
517
518         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
519
520         baud = uart_get_baud_rate(port, termios, old, 0,
521                 (port->uartclk / 14));
522         quot = __serial_get_clock_div(port->uartclk, baud);
523
524         spin_lock_irqsave(&port->lock, flags);
525
526         /* Ignore characters? */
527         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
528         if ((termios->c_cflag & CREAD) == 0)
529                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
530         else
531                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
532         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
533
534         __raw_writel(quot, LPC32XX_HSUART_RATE(port->membase));
535
536         uart_update_timeout(port, termios->c_cflag, baud);
537
538         spin_unlock_irqrestore(&port->lock, flags);
539 }
540
541 static const char *serial_lpc32xx_type(struct uart_port *port)
542 {
543         return MODNAME;
544 }
545
546 static void serial_lpc32xx_release_port(struct uart_port *port)
547 {
548         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
549                 if (port->flags & UPF_IOREMAP) {
550                         iounmap(port->membase);
551                         port->membase = NULL;
552                 }
553
554                 release_mem_region(port->mapbase, SZ_4K);
555         }
556 }
557
558 static int serial_lpc32xx_request_port(struct uart_port *port)
559 {
560         int ret = -ENODEV;
561
562         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
563                 ret = 0;
564
565                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
566                         ret = -EBUSY;
567                 else if (port->flags & UPF_IOREMAP) {
568                         port->membase = ioremap(port->mapbase, SZ_4K);
569                         if (!port->membase) {
570                                 release_mem_region(port->mapbase, SZ_4K);
571                                 ret = -ENOMEM;
572                         }
573                 }
574         }
575
576         return ret;
577 }
578
579 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
580 {
581         int ret;
582         struct lpc32xx_hsuart_port *p = (struct lpc32xx_hsuart_port *)port;
583
584         ret = serial_lpc32xx_request_port(port);
585         if (ret < 0)
586                 return;
587         port->type = PORT_UART00;
588         port->fifosize = 64;
589
590         __serial_uart_flush(port);
591
592         __raw_writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
593                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
594                 LPC32XX_HSUART_IIR(port->membase));
595
596         __raw_writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
597
598         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
599            and default FIFO trigger levels */
600         __raw_writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
601                 LPC32XX_HSU_OFFSET(p->fbit_sam) | LPC32XX_HSU_TMO_INACT_4B,
602                 LPC32XX_HSUART_CTRL(port->membase));
603 }
604
605 static int serial_lpc32xx_verify_port(struct uart_port *port,
606         struct serial_struct *ser)
607 {
608         int ret = 0;
609
610         if (ser->type != PORT_UART00)
611                 ret = -EINVAL;
612
613         return ret;
614 }
615
616 static struct uart_ops serial_lpc32xx_pops = {
617         .tx_empty       = serial_lpc32xx_tx_empty,
618         .set_mctrl      = serial_lpc32xx_set_mctrl,
619         .get_mctrl      = serial_lpc32xx_get_mctrl,
620         .stop_tx        = serial_lpc32xx_stop_tx,
621         .start_tx       = serial_lpc32xx_start_tx,
622         .stop_rx        = serial_lpc32xx_stop_rx,
623         .enable_ms      = serial_lpc32xx_enable_ms,
624         .break_ctl      = serial_lpc32xx_break_ctl,
625         .startup        = serial_lpc32xx_startup,
626         .shutdown       = serial_lpc32xx_shutdown,
627         .set_termios    = serial_lpc32xx_set_termios,
628         .type           = serial_lpc32xx_type,
629         .release_port   = serial_lpc32xx_release_port,
630         .request_port   = serial_lpc32xx_request_port,
631         .config_port    = serial_lpc32xx_config_port,
632         .verify_port    = serial_lpc32xx_verify_port,
633 };
634
635 /*
636  * Register a set of serial devices attached to a platform device
637  */
638 static int __devinit serial_hs_lpc32xx_probe(struct platform_device *pdev)
639 {
640         struct lpc32xx_hsuart_port *p = pdev->dev.platform_data;
641         struct lpc32xx_hsuart_port *pdr;
642         int i, ret = 0;
643
644         uarts_registered = 0;
645         for (i = 0; p && (p->port.flags != 0); i++) {
646                 pdr = &lpc32xx_hs_ports[i];
647                 memset(pdr, 0, sizeof(struct lpc32xx_hsuart_port));
648
649                 pdr->port.iotype        = p->port.iotype;
650                 pdr->port.membase       = p->port.membase;
651                 pdr->port.mapbase       = p->port.mapbase;
652                 pdr->port.irq           = p->port.irq;
653                 pdr->port.uartclk       = p->port.uartclk;
654                 pdr->port.regshift      = p->port.regshift;
655                 pdr->port.flags         = p->port.flags | UPF_FIXED_PORT;
656                 pdr->port.dev           = &pdev->dev;
657                 pdr->port.ops           = &serial_lpc32xx_pops;
658                 pdr->port.line          = p->port.line;
659                 pdr->fbit_sam           = p->fbit_sam;
660
661                 /* If First sample point is beyond limit,
662                  * set it to default value - 20
663                  */
664                 if((pdr->fbit_sam < 0) || (pdr->fbit_sam > 31)) {
665                         pdr->fbit_sam = 20;
666                 }
667
668                 spin_lock_init(&pdr->port.lock);
669
670                 uart_add_one_port(&lpc32xx_hs_reg, &pdr->port);
671                 p++;
672                 uarts_registered++;
673         }
674
675         return ret;
676 }
677
678 /*
679  * Remove serial ports registered against a platform device.
680  */
681 static int __devexit serial_hs_lpc32xx_remove(struct platform_device *pdev)
682 {
683         struct lpc32xx_hsuart_port *p;
684         int i;
685
686         for (i = 0; i < uarts_registered; i++) {
687                 p = &lpc32xx_hs_ports[i];
688
689                 if (p->port.dev == &pdev->dev)
690                         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
691         }
692
693         platform_set_drvdata(pdev, NULL);
694
695         return 0;
696 }
697
698
699 #if defined (CONFIG_PM)
700 static int serial_hs_lpc32xx_suspend(struct platform_device *dev, pm_message_t state)
701 {
702         int i;
703
704         for (i = 0; i < uarts_registered; i++) {
705                 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[i];
706
707                 if (p->port.type != PORT_UNKNOWN && p->port.dev == &dev->dev)
708                         uart_suspend_port(&lpc32xx_hs_reg, &p->port);
709         }
710
711         return 0;
712 }
713
714 static int serial_hs_lpc32xx_resume(struct platform_device *dev)
715 {
716         int i;
717
718         for (i = 0; i < uarts_registered; i++) {
719                 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[i];
720
721                 if (p->port.type != PORT_UNKNOWN && p->port.dev == &dev->dev)
722                         uart_resume_port(&lpc32xx_hs_reg, &p->port);
723         }
724
725         return 0;
726 }
727 #else
728 #define serial_hs_lpc32xx_suspend       NULL
729 #define serial_hs_lpc32xx_resume        NULL
730 #endif
731
732 static struct platform_driver serial_hs_lpc32xx_driver = {
733         .probe          = serial_hs_lpc32xx_probe,
734         .remove         = __devexit_p(serial_hs_lpc32xx_remove),
735         .suspend        = serial_hs_lpc32xx_suspend,
736         .resume         = serial_hs_lpc32xx_resume,
737         .driver         = {
738                 .name   = MODNAME,
739                 .owner  = THIS_MODULE,
740         },
741 };
742
743 static int __init lpc32xx_hsuart_init(void)
744 {
745         int ret;
746
747         ret = uart_register_driver(&lpc32xx_hs_reg);
748         if (ret == 0) {
749                 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
750                 if (ret)
751                         uart_unregister_driver(&lpc32xx_hs_reg);
752         }
753
754         return ret;
755 }
756
757 static void __exit lpc32xx_hsuart_exit(void)
758 {
759         platform_driver_unregister(&serial_hs_lpc32xx_driver);
760         uart_unregister_driver(&lpc32xx_hs_reg);
761 }
762
763 module_init(lpc32xx_hsuart_init);
764 module_exit(lpc32xx_hsuart_exit);
765
766 MODULE_AUTHOR("Kevin Wells (kevin.wells@nxp.com)");
767 MODULE_DESCRIPTION("NXP LPC32XX High speed UART driver");
768 MODULE_LICENSE("GPL");