drivers/serial/lpc32xx_hs.c

   1 /*
   2  * drivers/serial/lpc32xx_hs.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/ioport.h>
  21 #include <linux/init.h>
  22 #include <linux/console.h>
  23 #include <linux/sysrq.h>
  24 #include <linux/tty.h>
  25 #include <linux/tty_flip.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/serial.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/delay.h>
  30 #include <linux/nmi.h>
  31 #include <linux/io.h>
  32 #include <linux/irq.h>
  33
  34 /*
  35  * High speed UART register offsets
  36  */
  37 #define LPC32XX_HSUART_FIFO(x)                  (x + 0x00)
  38 #define LPC32XX_HSUART_LEVEL(x)                 (x + 0x04)
  39 #define LPC32XX_HSUART_IIR(x)                   (x + 0x08)
  40 #define LPC32XX_HSUART_CTRL(x)                  (x + 0x0C)
  41 #define LPC32XX_HSUART_RATE(x)                  (x + 0x10)
  42
  43 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
  44 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
  45 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
  46
  47 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
  48 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
  49
  50 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
  51 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
  52 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
  53 #define LPC32XX_HSU_FE_INT                      (1 << 3)
  54 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
  55 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
  56 #define LPC32XX_HSU_TX_INT                      (1 << 0)
  57
  58 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
  59 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
  60 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
  61 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
  62 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
  63 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
  64 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
  65 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
  66 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
  67 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
  68 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
  69 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
  70 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
  71 #define LPC32XX_HSU_BREAK                       (1 << 8)
  72 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
  73 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
  74 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
  75 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
  76 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
  77 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
  78 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
  79 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
  80 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
  81 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
  82 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
  83 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
  84 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
  85 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
  86
  87 #define MODNAME "lpc32xx_hsuart"
  88
  89 struct lpc32xx_hsuart_port {
  90         struct uart_port port;
  91 };
  92
  93 #define FIFO_READ_LIMIT 128
  94 #define MAX_PORTS 3
  95 #define LPC32XX_TTY_NAME "ttyTX"
  96 #define LPC32XX_TTY_MINOR_START 196
  97 #define LPC32XX_TTY_MAJOR 204
  98 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
  99
 100 #ifdef SERIAL_HS_LPC32XX_CONSOLE
 101 static void wait_for_xmit_empty(struct uart_port *port)
 102 {
 103         unsigned int timeout = 10000;
 104
 105         do {
 106                 if (LPC32XX_HSU_TX_LEV(__raw_readl(LPC32XX_HSUART_LEVEL(
 107                         port->membase))) == 0)
 108                         break;
 109                 if (--timeout == 0)
 110                         break;
 111                 udelay(1);
 112         } while (1);
 113 }
 114
 115 static void wait_for_xmit_ready(struct uart_port *port)
 116 {
 117         unsigned int timeout = 10000;
 118
 119         while (1) {
 120                 if (LPC32XX_HSU_TX_LEV(__raw_readl(LPC32XX_HSUART_LEVEL(
 121                         port->membase))) < 32)
 122                         break;
 123                 if (--timeout == 0)
 124                         break;
 125                 udelay(1);
 126         }
 127 }
 128
 129 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
 130 {
 131         wait_for_xmit_ready(port);
 132         __raw_writel((u32) ch, LPC32XX_HSUART_FIFO(port->membase));
 133 }
 134
 135 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
 136         unsigned int count) {
 137         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
 138         unsigned long flags;
 139         int locked = 1;
 140
 141         touch_nmi_watchdog();
 142         local_irq_save(flags);
 143         if (up->port.sysrq)
 144                 locked = 0;
 145         else if (oops_in_progress)
 146                 locked = spin_trylock(&up->port.lock);
 147         else
 148                 spin_lock(&up->port.lock);
 149
 150         uart_console_write(&up->port, s, count,
 151                 lpc32xx_hsuart_console_putchar);
 152         wait_for_xmit_empty(&up->port);
 153
 154         if (locked)
 155                 spin_unlock(&up->port.lock);
 156         local_irq_restore(flags);
 157 }
 158
 159 static int __init lpc32xx_hsuart_console_setup(struct console *co,
 160         char *options) {
 161         struct uart_port *port;
 162         int baud = 115200;
 163         int bits = 8;
 164         int parity = 'n';
 165         int flow = 'n';
 166
 167         if (co->index >= MAX_PORTS)
 168                 co->index = 0;
 169
 170         port = &lpc32xx_hs_ports[co->index].port;
 171         if (!port->membase)
 172                 return -ENODEV;
 173
 174         if (options)
 175                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 176
 177         return uart_set_options(port, co, baud, parity, bits, flow);
 178 }
 179
 180 static struct uart_driver lpc32xx_hsuart_reg;
 181 static struct console lpc32xx_hsuart_console = {
 182         .name           = LPC32XX_TTY_NAME,
 183         .write          = lpc32xx_hsuart_console_write,
 184         .device         = uart_console_device,
 185         .setup          = lpc32xx_hsuart_console_setup,
 186         .flags          = CON_PRINTBUFFER,
 187         .index          = -1,
 188         .data           = &lpc32xx_hsuart_reg,
 189 };
 190
 191 static int __init lpc32xx_hsuart_console_init(void)
 192 {
 193         register_console(&lpc32xx_hsuart_console);
 194         return 0;
 195 }
 196 console_initcall(lpc32xx_hsuart_console_init);
 197
 198 #define LPC32XX_HSUART_CONSOLE  (&lpc32xx_hsuart_console)
 199 #else
 200 #define LPC32XX_HSUART_CONSOLE NULL
 201 #endif
 202
 203 static struct uart_driver lpc32xx_hs_reg = {
 204         .owner          = THIS_MODULE,
 205         .driver_name    = MODNAME,
 206         .dev_name       = LPC32XX_TTY_NAME,
 207         .major          = LPC32XX_TTY_MAJOR,
 208         .minor          = LPC32XX_TTY_MINOR_START,
 209         .nr             = MAX_PORTS,
 210         .cons           = LPC32XX_HSUART_CONSOLE,
 211 };
 212 static int uarts_registered;
 213
 214 static unsigned int __serial_get_clock_div(unsigned long uartclk,
 215         unsigned long rate) {
 216         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
 217         u32 rate_diff;
 218
 219         /* Find the closest divider to get the desired clock rate */
 220         div = uartclk / rate;
 221         goodrate = hsu_rate = (div / 14) - 1;
 222         if (hsu_rate != 0)
 223                 hsu_rate--;
 224
 225         /* Tweak divider */
 226         l_hsu_rate = hsu_rate + 3;
 227         rate_diff = 0xFFFFFFFF;
 228
 229         while (hsu_rate < l_hsu_rate) {
 230                 comprate = uartclk / ((hsu_rate + 1) * 14);
 231                 if (abs(comprate - rate) < rate_diff) {
 232                         goodrate = hsu_rate;
 233                         rate_diff = abs(comprate - rate);
 234                 }
 235
 236                 hsu_rate++;
 237         }
 238         if (hsu_rate > 0xFF)
 239                 hsu_rate = 0xFF;
 240
 241         return goodrate;
 242 }
 243
 244 static void __serial_uart_flush(struct uart_port *port)
 245 {
 246         u32 tmp;
 247         int cnt = 0;
 248
 249         while ((__raw_readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
 250                 (cnt++ < FIFO_READ_LIMIT))
 251                 tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
 252 }
 253
 254 static void __serial_lpc32xx_rx(struct uart_port *port)
 255 {
 256         struct tty_struct *tty = port->state->port.tty;
 257         unsigned int tmp, flag;
 258
 259         /* Read data from FIFO and push into terminal */
 260         tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
 261         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
 262                 flag = TTY_NORMAL;
 263                 port->icount.rx++;
 264
 265                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
 266                         /* Framing error */
 267                         __raw_writel(LPC32XX_HSU_FE_INT,
 268                                 LPC32XX_HSUART_IIR(port->membase));
 269                         port->icount.frame++;
 270                         flag = TTY_FRAME;
 271                         tty_insert_flip_char(port->state->port.tty, 0,
 272                                 TTY_FRAME);
 273                         tty_schedule_flip(port->state->port.tty);
 274                 }
 275
 276                 tty_insert_flip_char(port->state->port.tty, (tmp & 0xFF),
 277                         flag);
 278
 279                 tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
 280         }
 281
 282         tty_flip_buffer_push(tty);
 283 }
 284
 285 static void __serial_lpc32xx_tx(struct uart_port *port)
 286 {
 287         struct circ_buf *xmit = &port->state->xmit;
 288         unsigned int tmp;
 289
 290         if (port->x_char) {
 291                 __raw_writel((u32) port->x_char,
 292                         LPC32XX_HSUART_FIFO(port->membase));
 293                 port->icount.tx++;
 294                 port->x_char = 0;
 295                 return;
 296         }
 297
 298         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 299                 goto exit_tx;
 300
 301         /* Transfer data */
 302         while (LPC32XX_HSU_TX_LEV(__raw_readl(
 303                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
 304                 __raw_writel((u32) xmit->buf[xmit->tail],
 305                         LPC32XX_HSUART_FIFO(port->membase));
 306                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 307                 port->icount.tx++;
 308                 if (uart_circ_empty(xmit))
 309                         break;
 310         }
 311
 312         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 313                 uart_write_wakeup(port);
 314
 315 exit_tx:
 316         if (uart_circ_empty(xmit)) {
 317                 tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
 318                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
 319                 __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 320         }
 321 }
 322
 323 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
 324 {
 325         struct uart_port *port = dev_id;
 326         u32 status;
 327
 328         spin_lock(&port->lock);
 329
 330         /* Read UART status and clear latched interrupts */
 331         status = __raw_readl(LPC32XX_HSUART_IIR(port->membase));
 332
 333         if (status & LPC32XX_HSU_BRK_INT) {
 334                 /* Break received */
 335                 __raw_writel(LPC32XX_HSU_BRK_INT,
 336                         LPC32XX_HSUART_IIR(port->membase));
 337                 port->icount.brk++;
 338                 uart_handle_break(port);
 339         }
 340
 341         /* Framing error */
 342         if (status & LPC32XX_HSU_FE_INT)
 343                 __raw_writel(LPC32XX_HSU_FE_INT,
 344                         LPC32XX_HSUART_IIR(port->membase));
 345
 346         if (status & LPC32XX_HSU_RX_OE_INT) {
 347                 /* Receive FIFO overrun */
 348                 __raw_writel(LPC32XX_HSU_RX_OE_INT,
 349                         LPC32XX_HSUART_IIR(port->membase));
 350                 port->icount.overrun++;
 351                 tty_insert_flip_char(port->state->port.tty, 0, TTY_OVERRUN);
 352                 tty_schedule_flip(port->state->port.tty);
 353         }
 354
 355         /* Data received? */
 356         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
 357                 __serial_lpc32xx_rx(port);
 358
 359         /* Transmit data request? */
 360         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
 361                 __raw_writel(LPC32XX_HSU_TX_INT,
 362                         LPC32XX_HSUART_IIR(port->membase));
 363                 __serial_lpc32xx_tx(port);
 364         }
 365
 366         spin_unlock(&port->lock);
 367
 368         return IRQ_HANDLED;
 369 }
 370
 371 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
 372 {
 373         unsigned int ret = 0;
 374
 375         if (LPC32XX_HSU_TX_LEV(__raw_readl(
 376                 LPC32XX_HSUART_LEVEL(port->membase))) == 0)
 377                 ret = TIOCSER_TEMT;
 378
 379         return ret;
 380 }
 381
 382 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
 383         unsigned int mctrl) {
 384         /* No signals are supported on HS UARTs */
 385 }
 386
 387 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
 388 {
 389         /* No signals are supported on HS UARTs */
 390         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 391 }
 392
 393 static void serial_lpc32xx_stop_tx(struct uart_port *port)
 394 {
 395         unsigned long flags;
 396         u32 tmp;
 397
 398         spin_lock_irqsave(&port->lock, flags);
 399
 400         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
 401         tmp &= ~LPC32XX_HSU_TX_INT_EN;
 402         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 403
 404         spin_unlock_irqrestore(&port->lock, flags);
 405 }
 406
 407 static void serial_lpc32xx_start_tx(struct uart_port *port)
 408 {
 409         unsigned long flags;
 410         u32 tmp;
 411
 412         spin_lock_irqsave(&port->lock, flags);
 413
 414         __serial_lpc32xx_tx(port);
 415         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
 416         tmp |= LPC32XX_HSU_TX_INT_EN;
 417         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 418
 419         spin_unlock_irqrestore(&port->lock, flags);
 420 }
 421
 422 static void serial_lpc32xx_stop_rx(struct uart_port *port)
 423 {
 424         unsigned long flags;
 425         u32 tmp;
 426
 427         spin_lock_irqsave(&port->lock, flags);
 428
 429         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
 430         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
 431         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 432
 433         __raw_writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
 434                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
 435
 436         spin_unlock_irqrestore(&port->lock, flags);
 437 }
 438
 439 static void serial_lpc32xx_enable_ms(struct uart_port *port)
 440 {
 441         /* Modem status is not supported */
 442 }
 443
 444 static void serial_lpc32xx_break_ctl(struct uart_port *port,
 445         int break_state) {
 446         unsigned long flags;
 447         u32 tmp;
 448
 449         spin_lock_irqsave(&port->lock, flags);
 450         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
 451         if (break_state != 0)
 452                 tmp |= LPC32XX_HSU_BREAK;
 453         else
 454                 tmp &= ~LPC32XX_HSU_BREAK;
 455         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 456         spin_unlock_irqrestore(&port->lock, flags);
 457 }
 458
 459 static int serial_lpc32xx_startup(struct uart_port *port)
 460 {
 461         int retval;
 462         u32 tmp;
 463
 464         __serial_uart_flush(port);
 465
 466         __raw_writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
 467                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
 468                 LPC32XX_HSUART_IIR(port->membase));
 469
 470         __raw_writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
 471
 472         /*
 473          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
 474          * and default FIFO trigger levels
 475          */
 476         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 477                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
 478         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 479
 480         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
 481                              0, MODNAME, port);
 482         if (retval)
 483                 return retval;
 484
 485         __raw_writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
 486                 LPC32XX_HSUART_CTRL(port->membase));
 487
 488         return 0;
 489 }
 490
 491 static void serial_lpc32xx_shutdown(struct uart_port *port)
 492 {
 493         u32 tmp;
 494
 495         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 496                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
 497         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 498
 499         free_irq(port->irq, port);
 500 }
 501
 502 static void serial_lpc32xx_set_termios(struct uart_port *port,
 503         struct ktermios *termios, struct ktermios *old)
 504 {
 505         unsigned long flags;
 506         unsigned int baud, quot;
 507         u32 tmp;
 508
 509         /* Always 8-bit, no parity, 1 stop bit */
 510         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
 511         termios->c_cflag |= CS8;
 512
 513         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
 514
 515         baud = uart_get_baud_rate(port, termios, old, 0,
 516                 (port->uartclk / 14));
 517         quot = __serial_get_clock_div(port->uartclk, baud);
 518
 519         spin_lock_irqsave(&port->lock, flags);
 520
 521         /* Ignore characters? */
 522         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
 523         if ((termios->c_cflag & CREAD) == 0)
 524                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
 525         else
 526                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
 527         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 528
 529         __raw_writel(quot, LPC32XX_HSUART_RATE(port->membase));
 530
 531         uart_update_timeout(port, termios->c_cflag, baud);
 532
 533         spin_unlock_irqrestore(&port->lock, flags);
 534 }
 535
 536 static const char *serial_lpc32xx_type(struct uart_port *port)
 537 {
 538         return MODNAME;
 539 }
 540
 541 static void serial_lpc32xx_release_port(struct uart_port *port)
 542 {
 543         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
 544                 if (port->flags & UPF_IOREMAP) {
 545                         iounmap(port->membase);
 546                         port->membase = NULL;
 547                 }
 548
 549                 release_mem_region(port->mapbase, SZ_4K);
 550         }
 551 }
 552
 553 static int serial_lpc32xx_request_port(struct uart_port *port)
 554 {
 555         int ret = -ENODEV;
 556
 557         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
 558                 ret = 0;
 559
 560                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
 561                         ret = -EBUSY;
 562                 else if (port->flags & UPF_IOREMAP) {
 563                         port->membase = ioremap(port->mapbase, SZ_4K);
 564                         if (!port->membase) {
 565                                 release_mem_region(port->mapbase, SZ_4K);
 566                                 ret = -ENOMEM;
 567                         }
 568                 }
 569         }
 570
 571         return ret;
 572 }
 573
 574 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
 575 {
 576         int ret;
 577
 578         ret = serial_lpc32xx_request_port(port);
 579         if (ret < 0)
 580                 return;
 581         port->type = PORT_UART00;
 582         port->fifosize = 64;
 583
 584         __serial_uart_flush(port);
 585
 586         __raw_writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
 587                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
 588                 LPC32XX_HSUART_IIR(port->membase));
 589
 590         __raw_writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
 591
 592         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
 593            and default FIFO trigger levels */
 594         __raw_writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 595                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
 596                 LPC32XX_HSUART_CTRL(port->membase));
 597 }
 598
 599 static int serial_lpc32xx_verify_port(struct uart_port *port,
 600         struct serial_struct *ser)
 601 {
 602         int ret = 0;
 603
 604         if (ser->type != PORT_UART00)
 605                 ret = -EINVAL;
 606
 607         return ret;
 608 }
 609
 610 static struct uart_ops serial_lpc32xx_pops = {
 611         .tx_empty       = serial_lpc32xx_tx_empty,
 612         .set_mctrl      = serial_lpc32xx_set_mctrl,
 613         .get_mctrl      = serial_lpc32xx_get_mctrl,
 614         .stop_tx        = serial_lpc32xx_stop_tx,
 615         .start_tx       = serial_lpc32xx_start_tx,
 616         .stop_rx        = serial_lpc32xx_stop_rx,
 617         .enable_ms      = serial_lpc32xx_enable_ms,
 618         .break_ctl      = serial_lpc32xx_break_ctl,
 619         .startup        = serial_lpc32xx_startup,
 620         .shutdown       = serial_lpc32xx_shutdown,
 621         .set_termios    = serial_lpc32xx_set_termios,
 622         .type           = serial_lpc32xx_type,
 623         .release_port   = serial_lpc32xx_release_port,
 624         .request_port   = serial_lpc32xx_request_port,
 625         .config_port    = serial_lpc32xx_config_port,
 626         .verify_port    = serial_lpc32xx_verify_port,
 627 };
 628
 629 /*
 630  * Register a set of serial devices attached to a platform device
 631  */
 632 static int __devinit serial_hs_lpc32xx_probe(struct platform_device *pdev)
 633 {
 634         struct uart_port *p = pdev->dev.platform_data;
 635         struct lpc32xx_hsuart_port *pdr;
 636         int i, ret = 0;
 637
 638         uarts_registered = 0;
 639         for (i = 0; p && (p->flags != 0); i++) {
 640                 pdr = &lpc32xx_hs_ports[i];
 641                 memset(pdr, 0, sizeof(struct lpc32xx_hsuart_port));
 642
 643                 pdr->port.iotype        = p->iotype;
 644                 pdr->port.membase       = p->membase;
 645                 pdr->port.mapbase       = p->mapbase;
 646                 pdr->port.irq           = p->irq;
 647                 pdr->port.uartclk       = p->uartclk;
 648                 pdr->port.regshift      = p->regshift;
 649                 pdr->port.flags         = p->flags | UPF_FIXED_PORT;
 650                 pdr->port.dev           = &pdev->dev;
 651                 pdr->port.ops           = &serial_lpc32xx_pops;
 652                 pdr->port.line          = p->line;
 653                 spin_lock_init(&pdr->port.lock);
 654
 655                 uart_add_one_port(&lpc32xx_hs_reg, &pdr->port);
 656                 p++;
 657                 uarts_registered++;
 658         }
 659
 660         return ret;
 661 }
 662
 663 /*
 664  * Remove serial ports registered against a platform device.
 665  */
 666 static int __devexit serial_hs_lpc32xx_remove(struct platform_device *pdev)
 667 {
 668         struct lpc32xx_hsuart_port *p;
 669         int i;
 670
 671         for (i = 0; i < uarts_registered; i++) {
 672                 p = &lpc32xx_hs_ports[i];
 673
 674                 if (p->port.dev == &pdev->dev)
 675                         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
 676         }
 677
 678         platform_set_drvdata(pdev, NULL);
 679
 680         return 0;
 681 }
 682
 683 static struct platform_driver serial_hs_lpc32xx_driver = {
 684         .probe          = serial_hs_lpc32xx_probe,
 685         .remove         = __devexit_p(serial_hs_lpc32xx_remove),
 686         /* Suspend and resume are not needed, as the UART autoclocks */
 687         .driver         = {
 688                 .name   = MODNAME,
 689                 .owner  = THIS_MODULE,
 690         },
 691 };
 692
 693 static int __init lpc32xx_hsuart_init(void)
 694 {
 695         int ret;
 696
 697         ret = uart_register_driver(&lpc32xx_hs_reg);
 698         if (ret == 0) {
 699                 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
 700                 if (ret)
 701                         uart_unregister_driver(&lpc32xx_hs_reg);
 702         }
 703
 704         return ret;
 705 }
 706
 707 static void __exit lpc32xx_hsuart_exit(void)
 708 {
 709         platform_driver_unregister(&serial_hs_lpc32xx_driver);
 710         uart_unregister_driver(&lpc32xx_hs_reg);
 711 }
 712
 713 module_init(lpc32xx_hsuart_init);
 714 module_exit(lpc32xx_hsuart_exit);
 715
 716 MODULE_AUTHOR("Kevin Wells (kevin.wells@nxp.com)");
 717 MODULE_DESCRIPTION("NXP LPC32XX High speed UART driver");
 718 MODULE_LICENSE("GPL");