serial: LPC32XX_hsuart: More spinlock issue corrections
[linux-2.6.34-lpc32xx.git] / drivers / serial / lpc32xx_hs.c
1 /*
2  * drivers/serial/lpc32xx_hs.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial.h>
28 #include <linux/platform_device.h>
29 #include <linux/delay.h>
30 #include <linux/nmi.h>
31 #include <linux/io.h>
32 #include <linux/irq.h>
33
34 /*
35  * High speed UART register offsets
36  */
37 #define LPC32XX_HSUART_FIFO(x)                  (x + 0x00)
38 #define LPC32XX_HSUART_LEVEL(x)                 (x + 0x04)
39 #define LPC32XX_HSUART_IIR(x)                   (x + 0x08)
40 #define LPC32XX_HSUART_CTRL(x)                  (x + 0x0C)
41 #define LPC32XX_HSUART_RATE(x)                  (x + 0x10)
42
43 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
44 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
45 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
46
47 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
48 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
49
50 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
51 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
52 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
53 #define LPC32XX_HSU_FE_INT                      (1 << 3)
54 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
55 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
56 #define LPC32XX_HSU_TX_INT                      (1 << 0)
57
58 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
59 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
60 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
61 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
62 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
63 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
64 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
65 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
66 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
67 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
68 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
69 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
70 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
71 #define LPC32XX_HSU_BREAK                       (1 << 8)
72 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
73 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
74 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
75 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
76 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
77 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
78 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
79 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
80 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
81 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
82 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
83 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
84 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
85 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
86
87 #define MODNAME "lpc32xx_hsuart"
88
89 struct lpc32xx_hsuart_port {
90         struct uart_port port;
91 };
92
93 #define FIFO_READ_LIMIT 128
94 #define MAX_PORTS 3
95 #define LPC32XX_TTY_NAME "ttyTX"
96 #define LPC32XX_TTY_MINOR_START 196
97 #define LPC32XX_TTY_MAJOR 204
98 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
99
100 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
101 static void wait_for_xmit_empty(struct uart_port *port)
102 {
103         unsigned int timeout = 10000;
104
105         do {
106                 if (LPC32XX_HSU_TX_LEV(__raw_readl(LPC32XX_HSUART_LEVEL(
107                         port->membase))) == 0)
108                         break;
109                 if (--timeout == 0)
110                         break;
111                 udelay(1);
112         } while (1);
113 }
114
115 static void wait_for_xmit_ready(struct uart_port *port)
116 {
117         unsigned int timeout = 10000;
118
119         while (1) {
120                 if (LPC32XX_HSU_TX_LEV(__raw_readl(LPC32XX_HSUART_LEVEL(
121                         port->membase))) < 32)
122                         break;
123                 if (--timeout == 0)
124                         break;
125                 udelay(1);
126         }
127 }
128
129 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
130 {
131         wait_for_xmit_ready(port);
132         __raw_writel((u32) ch, LPC32XX_HSUART_FIFO(port->membase));
133 }
134
135 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
136         unsigned int count) {
137         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
138         unsigned long flags;
139         int locked = 1;
140
141         touch_nmi_watchdog();
142         local_irq_save(flags);
143         if (up->port.sysrq)
144                 locked = 0;
145         else if (oops_in_progress)
146                 locked = spin_trylock(&up->port.lock);
147         else
148                 spin_lock(&up->port.lock);
149
150         uart_console_write(&up->port, s, count,
151                 lpc32xx_hsuart_console_putchar);
152         wait_for_xmit_empty(&up->port);
153
154         if (locked)
155                 spin_unlock(&up->port.lock);
156         local_irq_restore(flags);
157 }
158
159 static int __init lpc32xx_hsuart_console_setup(struct console *co,
160         char *options) {
161         struct uart_port *port;
162         int baud = 115200;
163         int bits = 8;
164         int parity = 'n';
165         int flow = 'n';
166
167         if (co->index >= MAX_PORTS)
168                 co->index = 0;
169
170         port = &lpc32xx_hs_ports[co->index].port;
171         if (!port->membase)
172                 return -ENODEV;
173
174         if (options)
175                 uart_parse_options(options, &baud, &parity, &bits, &flow);
176
177         return uart_set_options(port, co, baud, parity, bits, flow);
178 }
179
180 static struct uart_driver lpc32xx_hsuart_reg;
181 static struct console lpc32xx_hsuart_console = {
182         .name           = LPC32XX_TTY_NAME,
183         .write          = lpc32xx_hsuart_console_write,
184         .device         = uart_console_device,
185         .setup          = lpc32xx_hsuart_console_setup,
186         .flags          = CON_PRINTBUFFER,
187         .index          = -1,
188         .data           = &lpc32xx_hsuart_reg,
189 };
190
191 static int __init lpc32xx_hsuart_console_init(void)
192 {
193         register_console(&lpc32xx_hsuart_console);
194         return 0;
195 }
196 console_initcall(lpc32xx_hsuart_console_init);
197
198 #define LPC32XX_HSUART_CONSOLE  (&lpc32xx_hsuart_console)
199 #else
200 #define LPC32XX_HSUART_CONSOLE NULL
201 #endif
202
203 static struct uart_driver lpc32xx_hs_reg = {
204         .owner          = THIS_MODULE,
205         .driver_name    = MODNAME,
206         .dev_name       = LPC32XX_TTY_NAME,
207         .major          = LPC32XX_TTY_MAJOR,
208         .minor          = LPC32XX_TTY_MINOR_START,
209         .nr             = MAX_PORTS,
210         .cons           = LPC32XX_HSUART_CONSOLE,
211 };
212 static int uarts_registered;
213
214 static unsigned int __serial_get_clock_div(unsigned long uartclk,
215         unsigned long rate) {
216         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
217         u32 rate_diff;
218
219         /* Find the closest divider to get the desired clock rate */
220         div = uartclk / rate;
221         goodrate = hsu_rate = (div / 14) - 1;
222         if (hsu_rate != 0)
223                 hsu_rate--;
224
225         /* Tweak divider */
226         l_hsu_rate = hsu_rate + 3;
227         rate_diff = 0xFFFFFFFF;
228
229         while (hsu_rate < l_hsu_rate) {
230                 comprate = uartclk / ((hsu_rate + 1) * 14);
231                 if (abs(comprate - rate) < rate_diff) {
232                         goodrate = hsu_rate;
233                         rate_diff = abs(comprate - rate);
234                 }
235
236                 hsu_rate++;
237         }
238         if (hsu_rate > 0xFF)
239                 hsu_rate = 0xFF;
240
241         return goodrate;
242 }
243
244 static void __serial_uart_flush(struct uart_port *port)
245 {
246         u32 tmp;
247         int cnt = 0;
248
249         while ((__raw_readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
250                 (cnt++ < FIFO_READ_LIMIT))
251                 tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
252 }
253
254 static void __serial_lpc32xx_rx(struct uart_port *port)
255 {
256         unsigned int tmp, flag;
257
258         /* Read data from FIFO and push into terminal */
259         tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
260         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
261                 flag = TTY_NORMAL;
262                 port->icount.rx++;
263
264                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
265                         /* Framing error */
266                         __raw_writel(LPC32XX_HSU_FE_INT,
267                                 LPC32XX_HSUART_IIR(port->membase));
268                         port->icount.frame++;
269                         flag = TTY_FRAME;
270                         tty_insert_flip_char(port->state->port.tty, 0,
271                                 TTY_FRAME);
272                         tty_schedule_flip(port->state->port.tty);
273                 }
274
275                 tty_insert_flip_char(port->state->port.tty, (tmp & 0xFF),
276                         flag);
277
278                 tmp = __raw_readl(LPC32XX_HSUART_FIFO(port->membase));
279         }
280 }
281
282 static void __serial_lpc32xx_tx(struct uart_port *port)
283 {
284         struct circ_buf *xmit = &port->state->xmit;
285         unsigned int tmp;
286
287         if (port->x_char) {
288                 __raw_writel((u32) port->x_char,
289                         LPC32XX_HSUART_FIFO(port->membase));
290                 port->icount.tx++;
291                 port->x_char = 0;
292                 return;
293         }
294
295         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
296                 goto exit_tx;
297
298         /* Transfer data */
299         while (LPC32XX_HSU_TX_LEV(__raw_readl(
300                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
301                 __raw_writel((u32) xmit->buf[xmit->tail],
302                         LPC32XX_HSUART_FIFO(port->membase));
303                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
304                 port->icount.tx++;
305                 if (uart_circ_empty(xmit))
306                         break;
307         }
308
309         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
310                 uart_write_wakeup(port);
311
312 exit_tx:
313         if (uart_circ_empty(xmit)) {
314                 tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
315                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
316                 __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
317         }
318 }
319
320 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
321 {
322         struct uart_port *port = dev_id;
323         u32 status;
324
325         spin_lock(&port->lock);
326
327         /* Read UART status and clear latched interrupts */
328         status = __raw_readl(LPC32XX_HSUART_IIR(port->membase));
329
330         if (status & LPC32XX_HSU_BRK_INT) {
331                 /* Break received */
332                 __raw_writel(LPC32XX_HSU_BRK_INT,
333                         LPC32XX_HSUART_IIR(port->membase));
334                 port->icount.brk++;
335                 uart_handle_break(port);
336         }
337
338         /* Framing error */
339         if (status & LPC32XX_HSU_FE_INT)
340                 __raw_writel(LPC32XX_HSU_FE_INT,
341                         LPC32XX_HSUART_IIR(port->membase));
342
343         if (status & LPC32XX_HSU_RX_OE_INT) {
344                 /* Receive FIFO overrun */
345                 __raw_writel(LPC32XX_HSU_RX_OE_INT,
346                         LPC32XX_HSUART_IIR(port->membase));
347                 port->icount.overrun++;
348                 tty_insert_flip_char(port->state->port.tty, 0, TTY_OVERRUN);
349                 tty_schedule_flip(port->state->port.tty);
350         }
351
352         /* Data received? */
353         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
354                 __serial_lpc32xx_rx(port);
355                 spin_unlock(&port->lock);
356                 tty_flip_buffer_push(port->state->port.tty);
357                 spin_lock(&port->lock);
358         }
359
360         /* Transmit data request? */
361         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
362                 __raw_writel(LPC32XX_HSU_TX_INT,
363                         LPC32XX_HSUART_IIR(port->membase));
364                 __serial_lpc32xx_tx(port);
365         }
366
367         spin_unlock(&port->lock);
368
369         return IRQ_HANDLED;
370 }
371
372 /* port->lock is not held.  */
373 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
374 {
375         unsigned int ret = 0;
376
377         if (LPC32XX_HSU_TX_LEV(__raw_readl(
378                 LPC32XX_HSUART_LEVEL(port->membase))) == 0)
379                 ret = TIOCSER_TEMT;
380
381         return ret;
382 }
383
384 /* port->lock held by caller.  */
385 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
386         unsigned int mctrl) {
387         /* No signals are supported on HS UARTs */
388 }
389
390 /* port->lock is held by caller and interrupts are disabled.  */
391 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
392 {
393         /* No signals are supported on HS UARTs */
394         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
395 }
396
397 /* port->lock held by caller.  */
398 static void serial_lpc32xx_stop_tx(struct uart_port *port)
399 {
400         u32 tmp;
401
402         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
403         tmp &= ~LPC32XX_HSU_TX_INT_EN;
404         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
405 }
406
407 /* port->lock held by caller.  */
408 static void serial_lpc32xx_start_tx(struct uart_port *port)
409 {
410         u32 tmp;
411
412         __serial_lpc32xx_tx(port);
413         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
414         tmp |= LPC32XX_HSU_TX_INT_EN;
415         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
416 }
417
418 /* port->lock held by caller.  */
419 static void serial_lpc32xx_stop_rx(struct uart_port *port)
420 {
421         u32 tmp;
422
423         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
424         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
425         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
426
427         __raw_writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
428                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
429 }
430
431 /* port->lock held by caller.  */
432 static void serial_lpc32xx_enable_ms(struct uart_port *port)
433 {
434         /* Modem status is not supported */
435 }
436
437 /* port->lock is not held.  */
438 static void serial_lpc32xx_break_ctl(struct uart_port *port,
439         int break_state) {
440         unsigned long flags;
441         u32 tmp;
442
443         spin_lock_irqsave(&port->lock, flags);
444         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
445         if (break_state != 0)
446                 tmp |= LPC32XX_HSU_BREAK;
447         else
448                 tmp &= ~LPC32XX_HSU_BREAK;
449         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
450         spin_unlock_irqrestore(&port->lock, flags);
451 }
452
453 /* port->lock is not held.  */
454 static int serial_lpc32xx_startup(struct uart_port *port)
455 {
456         int retval;
457         unsigned long flags;
458         u32 tmp;
459
460         spin_lock_irqsave(&port->lock, flags);
461
462         __serial_uart_flush(port);
463
464         __raw_writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
465                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
466                 LPC32XX_HSUART_IIR(port->membase));
467
468         __raw_writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
469
470         /*
471          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
472          * and default FIFO trigger levels
473          */
474         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
475                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
476         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
477
478         spin_unlock_irqrestore(&port->lock, flags);
479
480         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
481                              0, MODNAME, port);
482         if (!retval)
483                 __raw_writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
484                         LPC32XX_HSUART_CTRL(port->membase));
485
486         return retval;
487 }
488
489 /* port->lock is not held.  */
490 static void serial_lpc32xx_shutdown(struct uart_port *port)
491 {
492         u32 tmp;
493         unsigned long flags;
494
495         spin_lock_irqsave(&port->lock, flags);
496
497         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
498                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
499         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
500
501         spin_unlock_irqrestore(&port->lock, flags);
502
503         free_irq(port->irq, port);
504 }
505
506 /* port->lock is not held.  */
507 static void serial_lpc32xx_set_termios(struct uart_port *port,
508         struct ktermios *termios, struct ktermios *old)
509 {
510         unsigned long flags;
511         unsigned int baud, quot;
512         u32 tmp;
513
514         /* Always 8-bit, no parity, 1 stop bit */
515         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
516         termios->c_cflag |= CS8;
517
518         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
519
520         baud = uart_get_baud_rate(port, termios, old, 0,
521                 (port->uartclk / 14));
522         quot = __serial_get_clock_div(port->uartclk, baud);
523
524         spin_lock_irqsave(&port->lock, flags);
525
526         /* Ignore characters? */
527         tmp = __raw_readl(LPC32XX_HSUART_CTRL(port->membase));
528         if ((termios->c_cflag & CREAD) == 0)
529                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
530         else
531                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
532         __raw_writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
533
534         __raw_writel(quot, LPC32XX_HSUART_RATE(port->membase));
535
536         uart_update_timeout(port, termios->c_cflag, baud);
537
538         spin_unlock_irqrestore(&port->lock, flags);
539 }
540
541 static const char *serial_lpc32xx_type(struct uart_port *port)
542 {
543         return MODNAME;
544 }
545
546 static void serial_lpc32xx_release_port(struct uart_port *port)
547 {
548         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
549                 if (port->flags & UPF_IOREMAP) {
550                         iounmap(port->membase);
551                         port->membase = NULL;
552                 }
553
554                 release_mem_region(port->mapbase, SZ_4K);
555         }
556 }
557
558 static int serial_lpc32xx_request_port(struct uart_port *port)
559 {
560         int ret = -ENODEV;
561
562         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
563                 ret = 0;
564
565                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
566                         ret = -EBUSY;
567                 else if (port->flags & UPF_IOREMAP) {
568                         port->membase = ioremap(port->mapbase, SZ_4K);
569                         if (!port->membase) {
570                                 release_mem_region(port->mapbase, SZ_4K);
571                                 ret = -ENOMEM;
572                         }
573                 }
574         }
575
576         return ret;
577 }
578
579 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
580 {
581         int ret;
582
583         ret = serial_lpc32xx_request_port(port);
584         if (ret < 0)
585                 return;
586         port->type = PORT_UART00;
587         port->fifosize = 64;
588
589         __serial_uart_flush(port);
590
591         __raw_writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
592                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
593                 LPC32XX_HSUART_IIR(port->membase));
594
595         __raw_writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
596
597         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
598            and default FIFO trigger levels */
599         __raw_writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
600                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
601                 LPC32XX_HSUART_CTRL(port->membase));
602 }
603
604 static int serial_lpc32xx_verify_port(struct uart_port *port,
605         struct serial_struct *ser)
606 {
607         int ret = 0;
608
609         if (ser->type != PORT_UART00)
610                 ret = -EINVAL;
611
612         return ret;
613 }
614
615 static struct uart_ops serial_lpc32xx_pops = {
616         .tx_empty       = serial_lpc32xx_tx_empty,
617         .set_mctrl      = serial_lpc32xx_set_mctrl,
618         .get_mctrl      = serial_lpc32xx_get_mctrl,
619         .stop_tx        = serial_lpc32xx_stop_tx,
620         .start_tx       = serial_lpc32xx_start_tx,
621         .stop_rx        = serial_lpc32xx_stop_rx,
622         .enable_ms      = serial_lpc32xx_enable_ms,
623         .break_ctl      = serial_lpc32xx_break_ctl,
624         .startup        = serial_lpc32xx_startup,
625         .shutdown       = serial_lpc32xx_shutdown,
626         .set_termios    = serial_lpc32xx_set_termios,
627         .type           = serial_lpc32xx_type,
628         .release_port   = serial_lpc32xx_release_port,
629         .request_port   = serial_lpc32xx_request_port,
630         .config_port    = serial_lpc32xx_config_port,
631         .verify_port    = serial_lpc32xx_verify_port,
632 };
633
634 /*
635  * Register a set of serial devices attached to a platform device
636  */
637 static int __devinit serial_hs_lpc32xx_probe(struct platform_device *pdev)
638 {
639         struct uart_port *p = pdev->dev.platform_data;
640         struct lpc32xx_hsuart_port *pdr;
641         int i, ret = 0;
642
643         uarts_registered = 0;
644         for (i = 0; p && (p->flags != 0); i++) {
645                 pdr = &lpc32xx_hs_ports[i];
646                 memset(pdr, 0, sizeof(struct lpc32xx_hsuart_port));
647
648                 pdr->port.iotype        = p->iotype;
649                 pdr->port.membase       = p->membase;
650                 pdr->port.mapbase       = p->mapbase;
651                 pdr->port.irq           = p->irq;
652                 pdr->port.uartclk       = p->uartclk;
653                 pdr->port.regshift      = p->regshift;
654                 pdr->port.flags         = p->flags | UPF_FIXED_PORT;
655                 pdr->port.dev           = &pdev->dev;
656                 pdr->port.ops           = &serial_lpc32xx_pops;
657                 pdr->port.line          = p->line;
658                 spin_lock_init(&pdr->port.lock);
659
660                 uart_add_one_port(&lpc32xx_hs_reg, &pdr->port);
661                 p++;
662                 uarts_registered++;
663         }
664
665         return ret;
666 }
667
668 /*
669  * Remove serial ports registered against a platform device.
670  */
671 static int __devexit serial_hs_lpc32xx_remove(struct platform_device *pdev)
672 {
673         struct lpc32xx_hsuart_port *p;
674         int i;
675
676         for (i = 0; i < uarts_registered; i++) {
677                 p = &lpc32xx_hs_ports[i];
678
679                 if (p->port.dev == &pdev->dev)
680                         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
681         }
682
683         platform_set_drvdata(pdev, NULL);
684
685         return 0;
686 }
687
688
689 #if defined (CONFIG_PM)
690 static int serial_hs_lpc32xx_suspend(struct platform_device *dev, pm_message_t state)
691 {
692         int i;
693
694         for (i = 0; i < uarts_registered; i++) {
695                 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[i];
696
697                 if (p->port.type != PORT_UNKNOWN && p->port.dev == &dev->dev)
698                         uart_suspend_port(&lpc32xx_hs_reg, &p->port);
699         }
700
701         return 0;
702 }
703
704 static int serial_hs_lpc32xx_resume(struct platform_device *dev)
705 {
706         int i;
707
708         for (i = 0; i < uarts_registered; i++) {
709                 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[i];
710
711                 if (p->port.type != PORT_UNKNOWN && p->port.dev == &dev->dev)
712                         uart_resume_port(&lpc32xx_hs_reg, &p->port);
713         }
714
715         return 0;
716 }
717 #else
718 #define serial_hs_lpc32xx_suspend       NULL
719 #define serial_hs_lpc32xx_resume        NULL
720 #endif
721
722 static struct platform_driver serial_hs_lpc32xx_driver = {
723         .probe          = serial_hs_lpc32xx_probe,
724         .remove         = __devexit_p(serial_hs_lpc32xx_remove),
725         .suspend        = serial_hs_lpc32xx_suspend,
726         .resume         = serial_hs_lpc32xx_resume,
727         .driver         = {
728                 .name   = MODNAME,
729                 .owner  = THIS_MODULE,
730         },
731 };
732
733 static int __init lpc32xx_hsuart_init(void)
734 {
735         int ret;
736
737         ret = uart_register_driver(&lpc32xx_hs_reg);
738         if (ret == 0) {
739                 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
740                 if (ret)
741                         uart_unregister_driver(&lpc32xx_hs_reg);
742         }
743
744         return ret;
745 }
746
747 static void __exit lpc32xx_hsuart_exit(void)
748 {
749         platform_driver_unregister(&serial_hs_lpc32xx_driver);
750         uart_unregister_driver(&lpc32xx_hs_reg);
751 }
752
753 module_init(lpc32xx_hsuart_init);
754 module_exit(lpc32xx_hsuart_exit);
755
756 MODULE_AUTHOR("Kevin Wells (kevin.wells@nxp.com)");
757 MODULE_DESCRIPTION("NXP LPC32XX High speed UART driver");
758 MODULE_LICENSE("GPL");