2 * drivers/rtc/rtc-lpc32xx.c
4 * Author: Kevin Wells <kevin.wells@nxp.com>
6 * Copyright (C) 2010 NXP Semiconductors
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/err.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/rtc.h>
25 #include <linux/spinlock.h>
26 #include <linux/types.h>
28 #include <linux/slab.h>
31 * Clock and Power control register offsets
33 #define RTC_UCOUNT(x) ((x) + 0x00)
34 #define RTC_DCOUNT(x) ((x) + 0x04)
35 #define RTC_MATCH0(x) ((x) + 0x08)
36 #define RTC_MATCH1(x) ((x) + 0x0C)
37 #define RTC_CTRL(x) ((x) + 0x10)
38 #define RTC_INTSTAT(x) ((x) + 0x14)
39 #define RTC_KEY(x) ((x) + 0x18)
40 #define RTC_SRAM(x, y) ((x) + 0x80 + ((y) * 4))
42 #define RTC_MATCH0_EN (1 << 0)
43 #define RTC_MATCH1_EN (1 << 1)
44 #define RTC_ONSW_MATCH0_EN (1 << 2)
45 #define RTC_ONSW_MATCH1_EN (1 << 3)
46 #define RTC_SW_RESET (1 << 4)
47 #define RTC_CNTR_DIS (1 << 6)
48 #define RTC_ONSW_FORCE_HIGH (1 << 7)
50 #define RTC_MATCH0_INT_STS (1 << 0)
51 #define RTC_MATCH1_INT_STS (1 << 1)
52 #define RTC_ONSW_INT_STS (1 << 2)
54 #define RTC_KEY_ONSW_LOADVAL 0xB5C13F27
56 static const char rtc_name[] = "rtc-lpc32xx";
58 struct lpc32xx_rtc_priv {
59 void __iomem *rtc_base;
62 struct rtc_device *rtc;
66 static inline void write_seconds(u32 iobase, unsigned long secs)
70 tmp = readl(RTC_CTRL(iobase));
72 writel(tmp, RTC_CTRL(iobase));
74 writel(secs, RTC_UCOUNT(iobase));
75 writel((0xFFFFFFFF - secs), RTC_DCOUNT(iobase));
78 writel(tmp, RTC_CTRL(iobase));
81 static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
83 unsigned long elapsed_sec;
84 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat = dev_get_drvdata(dev);
86 elapsed_sec = readl(RTC_UCOUNT(lpc32xx_rtc_dat->rtc_base));
88 rtc_time_to_tm(elapsed_sec, time);
93 static int lpc32xx_rtc_set_mmss(struct device *dev, unsigned long secs)
95 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat = dev_get_drvdata(dev);
97 spin_lock_irq(&lpc32xx_rtc_dat->lock);
98 write_seconds((u32) lpc32xx_rtc_dat->rtc_base, secs);
99 spin_unlock_irq(&lpc32xx_rtc_dat->lock);
104 static int lpc32xx_rtc_read_alarm(struct device *dev,
105 struct rtc_wkalrm *wkalrm)
107 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat = dev_get_drvdata(dev);
108 unsigned long alarmsecs;
110 alarmsecs = readl(RTC_MATCH0(lpc32xx_rtc_dat->rtc_base));
111 wkalrm->enabled = lpc32xx_rtc_dat->alarm_enabled;
113 rtc_time_to_tm(alarmsecs, &wkalrm->time);
118 static int lpc32xx_rtc_set_alarm(struct device *dev,
119 struct rtc_wkalrm *wkalrm)
121 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat = dev_get_drvdata(dev);
122 unsigned long alarmsecs;
125 ret = rtc_tm_to_time(&wkalrm->time, &alarmsecs);
127 dev_err(dev, "Failed to convert time: %d\n", ret);
131 spin_lock_irq(&lpc32xx_rtc_dat->lock);
133 if (lpc32xx_rtc_dat->alarm_enabled)
134 writel(~RTC_MATCH0_EN &
135 readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)),
136 RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
138 writel(alarmsecs, RTC_MATCH0(lpc32xx_rtc_dat->rtc_base));
139 lpc32xx_rtc_dat->alarm_enabled = wkalrm->enabled;
141 if (wkalrm->enabled) {
142 writel(RTC_MATCH0_INT_STS,
143 RTC_INTSTAT(lpc32xx_rtc_dat->rtc_base));
145 writel(RTC_MATCH0_EN |
146 readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)),
147 RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
150 spin_unlock_irq(&lpc32xx_rtc_dat->lock);
155 static int lpc32xx_rtc_proc(struct device *dev, struct seq_file *seq)
157 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat = dev_get_drvdata(dev);
160 tmp = readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
161 seq_printf(seq, "Alarm_IRQ\t: %s\n",
162 (tmp & RTC_MATCH0_EN) ? "yes" : "no");
167 static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
168 unsigned int enabled)
170 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat = dev_get_drvdata(dev);
173 if (!lpc32xx_rtc_dat->alarm_enabled) {
174 spin_lock_irq(&lpc32xx_rtc_dat->lock);
175 lpc32xx_rtc_dat->alarm_enabled = 1;
176 writel(RTC_MATCH0_EN |
177 readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)),
178 RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
179 spin_unlock_irq(&lpc32xx_rtc_dat->lock);
181 } else if (lpc32xx_rtc_dat->alarm_enabled) {
182 spin_lock_irq(&lpc32xx_rtc_dat->lock);
183 lpc32xx_rtc_dat->alarm_enabled = 0;
184 writel(~RTC_MATCH0_EN &
185 readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)),
186 RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
187 spin_unlock_irq(&lpc32xx_rtc_dat->lock);
193 static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
195 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat =
196 (struct lpc32xx_rtc_priv *) dev;
198 spin_lock(&lpc32xx_rtc_dat->lock);
200 /* If the alarm isn't disabled, the match will keep occuring, so
202 writel(readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)) &
203 ~RTC_MATCH0_EN, RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
205 /* Write a large value to the match value so the RTC won't
206 keep firing the match status */
207 writel(0xFFFFFFFF, RTC_MATCH0(lpc32xx_rtc_dat->rtc_base));
208 writel(RTC_MATCH0_INT_STS,
209 RTC_INTSTAT(lpc32xx_rtc_dat->rtc_base));
211 rtc_update_irq(lpc32xx_rtc_dat->rtc, 1, RTC_IRQF | RTC_AF);
213 spin_unlock(&lpc32xx_rtc_dat->lock);
218 static const struct rtc_class_ops lpc32xx_rtc_ops = {
219 .read_time = lpc32xx_rtc_read_time,
220 .set_mmss = lpc32xx_rtc_set_mmss,
221 .read_alarm = lpc32xx_rtc_read_alarm,
222 .set_alarm = lpc32xx_rtc_set_alarm,
223 .proc = lpc32xx_rtc_proc,
224 .alarm_irq_enable = lpc32xx_rtc_alarm_irq_enable,
227 static int __devinit lpc32xx_rtc_probe(struct platform_device *pdev)
229 struct resource *res, *mem = NULL;
230 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat = NULL;
234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
236 dev_err(&pdev->dev, "Can't get memory resource\n");
240 rtcirq = platform_get_irq(pdev, 0);
241 if ((rtcirq < 0) || (rtcirq >= NR_IRQS)) {
242 dev_err(&pdev->dev, "Can't get interrupt resource\n");
246 lpc32xx_rtc_dat = kzalloc(sizeof(struct lpc32xx_rtc_priv),
248 if (unlikely(!lpc32xx_rtc_dat)) {
249 dev_err(&pdev->dev, "Can't allocate memory\n");
252 lpc32xx_rtc_dat->irq = rtcirq;
254 mem = request_mem_region(res->start, resource_size(res), pdev->name);
256 dev_err(&pdev->dev, "RTC registers are not free\n");
261 lpc32xx_rtc_dat->rtc_base = ioremap(res->start,
262 res->end - res->start + 1);
263 if (!lpc32xx_rtc_dat->rtc_base) {
264 dev_err(&pdev->dev, "Can't map memory\n");
269 spin_lock_init(&lpc32xx_rtc_dat->lock);
271 /* If RTC has never been previously setup, then set it up
273 if (readl(RTC_KEY(lpc32xx_rtc_dat->rtc_base)) !=
274 RTC_KEY_ONSW_LOADVAL) {
275 spin_lock_irq(&lpc32xx_rtc_dat->lock);
276 tmp = readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
277 tmp &= ~(RTC_SW_RESET | RTC_CNTR_DIS | RTC_MATCH0_EN |
278 RTC_MATCH1_EN | RTC_ONSW_MATCH0_EN |
279 RTC_ONSW_MATCH1_EN | RTC_ONSW_FORCE_HIGH);
280 writel(tmp, RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
282 /* Clear latched interrupt states */
283 writel(0xFFFFFFFF, RTC_MATCH0(lpc32xx_rtc_dat->rtc_base));
284 writel(RTC_MATCH0_INT_STS | RTC_MATCH1_INT_STS |
286 RTC_INTSTAT(lpc32xx_rtc_dat->rtc_base));
288 /* Write key value to RTC so it won't reload on reset */
289 writel(RTC_KEY_ONSW_LOADVAL,
290 RTC_KEY(lpc32xx_rtc_dat->rtc_base));
292 spin_unlock_irq(&lpc32xx_rtc_dat->lock);
293 } else if (readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)) & RTC_MATCH0_EN)
294 lpc32xx_rtc_dat->alarm_enabled = 1;
296 platform_set_drvdata(pdev, lpc32xx_rtc_dat);
298 device_init_wakeup(&pdev->dev, 1);
299 lpc32xx_rtc_dat->rtc = rtc_device_register(rtc_name, &pdev->dev,
300 &lpc32xx_rtc_ops, THIS_MODULE);
301 if (IS_ERR(lpc32xx_rtc_dat->rtc)) {
302 dev_err(&pdev->dev, "Can't get RTC\n");
303 retval = PTR_ERR(lpc32xx_rtc_dat->rtc);
307 retval = request_irq(lpc32xx_rtc_dat->irq, lpc32xx_rtc_alarm_interrupt,
308 0, "rtcalarm", lpc32xx_rtc_dat);
310 dev_err(&pdev->dev, "Can't request interrupt\n");
317 rtc_device_unregister(lpc32xx_rtc_dat->rtc);
319 iounmap(lpc32xx_rtc_dat->rtc_base);
321 release_resource(mem);
323 kfree(lpc32xx_rtc_dat);
328 static int __devexit lpc32xx_rtc_remove(struct platform_device *pdev)
330 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat =
331 platform_get_drvdata(pdev);
333 free_irq(lpc32xx_rtc_dat->irq, pdev);
334 rtc_device_unregister(lpc32xx_rtc_dat->rtc);
335 iounmap(lpc32xx_rtc_dat->rtc_base);
336 release_resource(dev_get_drvdata(&lpc32xx_rtc_dat->rtc->dev));
337 kfree(lpc32xx_rtc_dat);
343 /* Turn off the alarm if it should not be a wake source. */
344 static int lpc32xx_rtc_suspend(struct device *dev)
346 struct platform_device *pdev = to_platform_device(dev);
347 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat =
348 platform_get_drvdata(pdev);
351 spin_lock_irq(&lpc32xx_rtc_dat->lock);
352 tmp = readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
354 if (device_may_wakeup(&pdev->dev))
355 tmp |= RTC_MATCH0_EN;
357 tmp &= ~RTC_MATCH0_EN;
359 writel(tmp, RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
360 spin_unlock_irq(&lpc32xx_rtc_dat->lock);
365 /* Enable the alarm if it should be enabled (in case it was disabled to
366 * prevent use as a wake source).
368 static int lpc32xx_rtc_resume(struct device *dev)
370 struct platform_device *pdev = to_platform_device(dev);
371 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat =
372 platform_get_drvdata(pdev);
374 if (lpc32xx_rtc_dat->alarm_enabled) {
375 spin_lock_irq(&lpc32xx_rtc_dat->lock);
377 writel(RTC_MATCH0_EN |
378 readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)),
379 RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
380 spin_unlock_irq(&lpc32xx_rtc_dat->lock);
386 /* Unconditionally disable the alarm */
387 static int lpc32xx_rtc_freeze(struct device *dev)
389 struct platform_device *pdev = to_platform_device(dev);
390 struct lpc32xx_rtc_priv *lpc32xx_rtc_dat =
391 platform_get_drvdata(pdev);
393 spin_lock_irq(&lpc32xx_rtc_dat->lock);
395 writel(~RTC_MATCH0_EN &
396 readl(RTC_CTRL(lpc32xx_rtc_dat->rtc_base)),
397 RTC_CTRL(lpc32xx_rtc_dat->rtc_base));
402 #define lpc32xx_rtc_suspend NULL
403 #define lpc32xx_rtc_resume NULL
404 #define lpc32xx_rtc_freeze NULL
407 static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
408 .suspend = lpc32xx_rtc_suspend,
409 .resume = lpc32xx_rtc_resume,
410 .freeze = lpc32xx_rtc_freeze,
411 .thaw = lpc32xx_rtc_resume,
412 .restore = lpc32xx_rtc_resume
415 static struct platform_driver lpc32xx_rtc_driver = {
416 .probe = lpc32xx_rtc_probe,
417 .remove = __devexit_p(lpc32xx_rtc_remove),
420 .pm = &lpc32xx_rtc_pm_ops,
424 static int __init lpc32xx_rtc_init(void)
426 return platform_driver_register(&lpc32xx_rtc_driver);
429 static void __exit lpc32xx_rtc_exit(void)
431 platform_driver_unregister(&lpc32xx_rtc_driver);
434 module_init(lpc32xx_rtc_init);
435 module_exit(lpc32xx_rtc_exit);
437 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com");
438 MODULE_DESCRIPTION("LPC32XX RTC Driver");
439 MODULE_LICENSE("GPL");