Update 1 of the 2.6.34 linux kernel release
[linux-2.6.34-lpc32xx.git] / drivers / input / touchscreen / lpc32xx_ts.c
1 /*
2  * drivers/input/touchscreen/lpc32xx_tsc.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/platform_device.h>
20 #include <linux/init.h>
21 #include <linux/input.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 /*
29  * Touchscreen controller register offsets
30  */
31 #define LPC32XX_TSC_STAT(x)                     ((x) + 0x00)
32 #define LPC32XX_TSC_SEL(x)                      ((x) + 0x04)
33 #define LPC32XX_TSC_CON(x)                      ((x) + 0x08)
34 #define LPC32XX_TSC_FIFO(x)                     ((x) + 0x0C)
35 #define LPC32XX_TSC_DTR(x)                      ((x) + 0x10)
36 #define LPC32XX_TSC_RTR(x)                      ((x) + 0x14)
37 #define LPC32XX_TSC_UTR(x)                      ((x) + 0x18)
38 #define LPC32XX_TSC_TTR(x)                      ((x) + 0x1C)
39 #define LPC32XX_TSC_DXP(x)                      ((x) + 0x20)
40 #define LPC32XX_TSC_MIN_X(x)                    ((x) + 0x24)
41 #define LPC32XX_TSC_MAX_X(x)                    ((x) + 0x28)
42 #define LPC32XX_TSC_MIN_Y(x)                    ((x) + 0x2C)
43 #define LPC32XX_TSC_MAX_Y(x)                    ((x) + 0x30)
44 #define LPC32XX_TSC_AUX_UTR(x)                  ((x) + 0x34)
45 #define LPC32XX_TSC_AUX_MIN(x)                  ((x) + 0x38)
46 #define LPC32XX_TSC_AUX_MAX(x)                  ((x) + 0x3C)
47
48 #define LPC32XX_TSC_STAT_FIFO_OVRRN             (1 << 8)
49 #define LPC32XX_TSC_STAT_FIFO_EMPTY             (1 << 7)
50
51 #define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4        (0x1 << 11)
52 #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s)     ((10 - s) << 7)
53 #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s)     ((10 - s) << 4)
54 #define LPC32XX_TSC_ADCCON_POWER_UP             (1 << 2)
55 #define LPC32XX_TSC_ADCCON_AUTO_EN              (1 << 0)
56
57 #define LPC32XX_TSC_FIFO_TS_P_LEVEL             (1 << 31)
58 #define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x)     (((x) & 0x03FF0000) >> 16)
59 #define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y)     ((y) & 0x000003FF)
60
61 #define LPC32XX_TSC_ADCDAT_VALUE_MASK           0x000003FF
62
63 #define MOD_NAME "lpc32xx-ts"
64
65 struct lpc32xx_tsc_t {
66         struct input_dev *dev;
67         void __iomem *tsc_base;
68         int irq;
69         struct clk *clk;
70         int suspended;
71 };
72
73 static void lpc32xx_fifo_clear(struct lpc32xx_tsc_t *lpc32xx_tsc_dat)
74 {
75         while (!(__raw_readl(LPC32XX_TSC_STAT(lpc32xx_tsc_dat->tsc_base)) &
76                 LPC32XX_TSC_STAT_FIFO_EMPTY))
77                 __raw_readl(LPC32XX_TSC_FIFO(lpc32xx_tsc_dat->tsc_base));
78 }
79
80 static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id)
81 {
82         u32 tmp, rv[4], xs[4], ys[4];
83         int idx;
84         struct lpc32xx_tsc_t *lpc32xx_tsc_dat =
85                 (struct lpc32xx_tsc_t *) dev_id;
86         struct input_dev *input = lpc32xx_tsc_dat->dev;
87
88         tmp = __raw_readl(LPC32XX_TSC_STAT(lpc32xx_tsc_dat->tsc_base));
89
90         if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) {
91                 /* FIFO overflow - throw away samples */
92                 lpc32xx_fifo_clear(lpc32xx_tsc_dat);
93                 return IRQ_HANDLED;
94         }
95
96         idx = 0;
97         while ((idx < 4) &&
98                 (!(__raw_readl(LPC32XX_TSC_STAT(lpc32xx_tsc_dat->tsc_base)) &
99                 LPC32XX_TSC_STAT_FIFO_EMPTY))) {
100                 tmp = __raw_readl(LPC32XX_TSC_FIFO(lpc32xx_tsc_dat->tsc_base));
101                 xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
102                         LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp);
103                 ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
104                         LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp);
105                 rv[idx] = tmp;
106                 idx++;
107         }
108
109         /* Data is only valid if pen is still down */
110         if ((!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL)) && (idx == 4)) {
111                 input_report_abs(input, ABS_X, ((xs[1] + xs[2]) / 2));
112                 input_report_abs(input, ABS_Y, ((ys[1] + ys[2]) / 2));
113                 input_report_abs(input, ABS_PRESSURE, 1);
114                 input_report_key(input, BTN_TOUCH, 1);
115         } else {
116                 input_report_abs(input, ABS_PRESSURE, 0);
117                 input_report_key(input, BTN_TOUCH, 0);
118         }
119
120         input_sync(input);
121
122         return IRQ_HANDLED;
123 }
124
125 static void stop_tsc(struct lpc32xx_tsc_t *lpc32xx_tsc_dat)
126 {
127         u32 tmp;
128
129         /* Disable auto mode */
130         tmp = __raw_readl(LPC32XX_TSC_CON(lpc32xx_tsc_dat->tsc_base));
131         tmp &= ~LPC32XX_TSC_ADCCON_AUTO_EN;
132         __raw_writel(tmp, LPC32XX_TSC_CON(lpc32xx_tsc_dat->tsc_base));
133 }
134
135 static void setup_tsc(struct lpc32xx_tsc_t *lpc32xx_tsc_dat)
136 {
137         u32 tmp;
138
139         tmp = __raw_readl(LPC32XX_TSC_CON(lpc32xx_tsc_dat->tsc_base));
140         tmp &= ~LPC32XX_TSC_ADCCON_POWER_UP;
141         __raw_writel(tmp, LPC32XX_TSC_CON(lpc32xx_tsc_dat->tsc_base));
142
143         /* Set the TSC FIFO depth to 4 samples @ 10-bits sample */
144         tmp = (LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 |
145                 LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) |
146                 LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10));
147         __raw_writel(tmp, LPC32XX_TSC_CON(lpc32xx_tsc_dat->tsc_base));
148
149         __raw_writel(0x0284, LPC32XX_TSC_SEL(lpc32xx_tsc_dat->tsc_base));
150         __raw_writel(0x0000, LPC32XX_TSC_MIN_X(lpc32xx_tsc_dat->tsc_base));
151         __raw_writel(0x03FF, LPC32XX_TSC_MAX_X(lpc32xx_tsc_dat->tsc_base));
152         __raw_writel(0x0000, LPC32XX_TSC_MIN_Y(lpc32xx_tsc_dat->tsc_base));
153         __raw_writel(0x03FF, LPC32XX_TSC_MAX_Y(lpc32xx_tsc_dat->tsc_base));
154         __raw_writel(0x0000, LPC32XX_TSC_AUX_UTR(lpc32xx_tsc_dat->tsc_base));
155         __raw_writel(0x0000, LPC32XX_TSC_AUX_MIN(lpc32xx_tsc_dat->tsc_base));
156         __raw_writel(0x0000, LPC32XX_TSC_AUX_MAX(lpc32xx_tsc_dat->tsc_base));
157         __raw_writel(0x2, LPC32XX_TSC_RTR(lpc32xx_tsc_dat->tsc_base));
158         __raw_writel(446, LPC32XX_TSC_UTR(lpc32xx_tsc_dat->tsc_base));
159         __raw_writel(0x2, LPC32XX_TSC_DTR(lpc32xx_tsc_dat->tsc_base));
160         __raw_writel(0x10, LPC32XX_TSC_TTR(lpc32xx_tsc_dat->tsc_base));
161         __raw_writel(0x4, LPC32XX_TSC_DXP(lpc32xx_tsc_dat->tsc_base));
162
163         /*
164          * Set sample rate to about 60Hz, this rate is based on the
165          * RTC clock, which should be a stable 32768Hz
166          */
167         __raw_writel(88, LPC32XX_TSC_UTR(lpc32xx_tsc_dat->tsc_base));
168
169         lpc32xx_fifo_clear(lpc32xx_tsc_dat);
170
171         tmp = __raw_readl(LPC32XX_TSC_CON(lpc32xx_tsc_dat->tsc_base));
172         tmp |= LPC32XX_TSC_ADCCON_AUTO_EN;
173         __raw_writel(tmp, LPC32XX_TSC_CON(lpc32xx_tsc_dat->tsc_base));
174 }
175
176 static int __devinit lpc32xx_ts_probe(struct platform_device *pdev)
177 {
178         struct lpc32xx_tsc_t *lpc32xx_tsc_dat = NULL;
179         struct resource *res;
180         int retval = -ENODEV;
181
182         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
183         if (!res) {
184                 dev_err(&pdev->dev, "failed to get platform I/O memory\n");
185                 retval = -EBUSY;
186                 goto errout;
187         }
188
189         lpc32xx_tsc_dat = kzalloc(sizeof(struct lpc32xx_tsc_t), GFP_KERNEL);
190         if (unlikely(!lpc32xx_tsc_dat)) {
191                 dev_err(&pdev->dev, "failed allocating memory\n");
192                 retval = -ENOMEM;
193                 goto errout;
194         }
195
196         lpc32xx_tsc_dat->tsc_base = ioremap(res->start,
197                 res->end - res->start + 1);
198         if (!lpc32xx_tsc_dat->tsc_base) {
199                 dev_err(&pdev->dev, "failed mapping memory\n");
200                 retval = -EBUSY;
201                 goto errout;
202         }
203
204         lpc32xx_tsc_dat->dev = input_allocate_device();
205         if (!lpc32xx_tsc_dat->dev) {
206                 dev_err(&pdev->dev, "failed allocating input device\n");
207                 retval = -ENOMEM;
208                 goto errout;
209         }
210
211         lpc32xx_tsc_dat->clk = clk_get(&pdev->dev, NULL);
212         if (IS_ERR(lpc32xx_tsc_dat->clk)) {
213                 dev_err(&pdev->dev, "failed getting clock\n");
214                 goto errout;
215         }
216         clk_enable(lpc32xx_tsc_dat->clk);
217
218         setup_tsc(lpc32xx_tsc_dat);
219
220         lpc32xx_tsc_dat->irq = platform_get_irq(pdev, 0);
221         if ((lpc32xx_tsc_dat->irq < 0) || (lpc32xx_tsc_dat->irq >= NR_IRQS)) {
222                 dev_err(&pdev->dev, "failed getting interrupt resource\n");
223                 retval = -EINVAL;
224                 goto errout;
225         }
226
227         retval = request_irq(lpc32xx_tsc_dat->irq, lpc32xx_ts_interrupt,
228                 0, MOD_NAME, lpc32xx_tsc_dat);
229         if (retval < 0) {
230                 dev_err(&pdev->dev, "failed requesting interrupt\n");
231                 goto err_free_irq;
232         }
233
234         platform_set_drvdata(pdev, lpc32xx_tsc_dat);
235
236         lpc32xx_tsc_dat->dev->name = MOD_NAME;
237         lpc32xx_tsc_dat->dev->phys = "lpc32xx/input0";
238         lpc32xx_tsc_dat->dev->id.bustype = BUS_HOST;
239         lpc32xx_tsc_dat->dev->id.vendor = 0x0001;
240         lpc32xx_tsc_dat->dev->id.product = 0x0002;
241         lpc32xx_tsc_dat->dev->id.version = 0x0100;
242         lpc32xx_tsc_dat->dev->dev.parent = &pdev->dev;
243
244         lpc32xx_tsc_dat->dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
245         lpc32xx_tsc_dat->dev->keybit[BIT_WORD(BTN_TOUCH)] =
246                 BIT_MASK(BTN_TOUCH);
247         input_set_abs_params(lpc32xx_tsc_dat->dev, ABS_X, 0, 1023, 0, 0);
248         input_set_abs_params(lpc32xx_tsc_dat->dev, ABS_Y, 0, 1023, 0, 0);
249         input_set_abs_params(lpc32xx_tsc_dat->dev, ABS_PRESSURE, 0, 1, 0, 0);
250
251         retval = input_register_device(lpc32xx_tsc_dat->dev);
252         if (retval) {
253                 dev_err(&pdev->dev, "failed registering input device\n");
254                 goto err_free_irq;
255         }
256
257         device_init_wakeup(&pdev->dev, 1);
258
259         return 0;
260
261 err_free_irq:
262         stop_tsc(lpc32xx_tsc_dat);
263         platform_set_drvdata(pdev, NULL);
264         free_irq(lpc32xx_tsc_dat->irq, lpc32xx_tsc_dat->dev);
265
266 errout:
267         if (lpc32xx_tsc_dat) {
268                 if (lpc32xx_tsc_dat->clk) {
269                         clk_disable(lpc32xx_tsc_dat->clk);
270                         clk_put(lpc32xx_tsc_dat->clk);
271                 }
272
273                 if (lpc32xx_tsc_dat->dev)
274                         input_free_device(lpc32xx_tsc_dat->dev);
275
276                 if (lpc32xx_tsc_dat->tsc_base)
277                         iounmap(lpc32xx_tsc_dat->tsc_base);
278
279                 kfree(lpc32xx_tsc_dat);
280         }
281
282         return retval;
283 }
284
285 static int __devexit lpc32xx_ts_remove(struct platform_device *pdev)
286 {
287         struct lpc32xx_tsc_t *lpc32xx_tsc_dat = platform_get_drvdata(pdev);
288
289         stop_tsc(lpc32xx_tsc_dat);
290         free_irq(lpc32xx_tsc_dat->irq, lpc32xx_tsc_dat->dev);
291         platform_set_drvdata(pdev, NULL);
292         input_unregister_device(lpc32xx_tsc_dat->dev);
293
294         if (lpc32xx_tsc_dat->clk) {
295                 clk_disable(lpc32xx_tsc_dat->clk);
296                 clk_put(lpc32xx_tsc_dat->clk);
297         }
298
299         if (lpc32xx_tsc_dat->tsc_base)
300                 iounmap(lpc32xx_tsc_dat->tsc_base);
301
302         kfree(lpc32xx_tsc_dat);
303
304         return 0;
305 }
306
307 #if defined (CONFIG_PM)
308 static int lpc32xx_ts_suspend(struct device *dev)
309 {
310         struct lpc32xx_tsc_t *lpc32xx_tsc_dat = dev_get_drvdata(dev);
311
312         if (device_may_wakeup(dev))
313                 enable_irq_wake(lpc32xx_tsc_dat->irq);
314         else {
315                 lpc32xx_tsc_dat->suspended = 1;
316                 stop_tsc(lpc32xx_tsc_dat);
317                 clk_disable(lpc32xx_tsc_dat->clk);
318         }
319
320         return 0;
321 }
322
323 static int lpc32xx_ts_resume(struct device *dev)
324 {
325         struct lpc32xx_tsc_t *lpc32xx_tsc_dat = dev_get_drvdata(dev);
326
327         if (lpc32xx_tsc_dat->suspended) {
328                 clk_enable(lpc32xx_tsc_dat->clk);
329                 setup_tsc(lpc32xx_tsc_dat);
330                 lpc32xx_tsc_dat->suspended = 0;
331         } else
332                 disable_irq_wake(lpc32xx_tsc_dat->irq);
333
334         return 0;
335 }
336
337 static const struct dev_pm_ops lpc32xx_ts_pm_ops = {
338         .suspend        = lpc32xx_ts_suspend,
339         .resume         = lpc32xx_ts_resume,
340 };
341 #define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops)
342 #else
343 #define LPC32XX_TS_PM_OPS NULL
344 #endif
345
346 static struct platform_driver lpc32xx_ts_driver = {
347         .probe          = lpc32xx_ts_probe,
348         .remove         = __devexit_p(lpc32xx_ts_remove),
349         .driver         = {
350                 .name   = MOD_NAME,
351                 .owner  = THIS_MODULE,
352                 .pm     = LPC32XX_TS_PM_OPS,
353         },
354 };
355
356 static int __init lpc32xx_ts_init(void)
357 {
358         return platform_driver_register(&lpc32xx_ts_driver);
359 }
360
361 static void __exit lpc32xx_ts_exit(void)
362 {
363         platform_driver_unregister(&lpc32xx_ts_driver);
364 }
365
366 module_init(lpc32xx_ts_init);
367 module_exit(lpc32xx_ts_exit);
368
369 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com");
370 MODULE_DESCRIPTION("LPC32XX TSC Driver");
371 MODULE_LICENSE("GPL");