i2c:lpc32xx:Fix I2C PNX timeout crash issue
[linux-2.6.34-lpc32xx.git] / drivers / i2c / busses / i2c-pnx.c
1 /*
2  * Provides I2C support for Philips PNX010x/PNX4008 boards.
3  *
4  * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
5  *          Vitaly Wool <vwool@ru.mvista.com>
6  *
7  * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
8  * the terms of the GNU General Public License version 2. This program
9  * is licensed "as is" without any warranty of any kind, whether express
10  * or implied.
11  */
12
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/timer.h>
19 #include <linux/completion.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c-pnx.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/slab.h>
26
27 #include <mach/hardware.h>
28 #include <mach/i2c.h>
29
30 #define I2C_PNX_TIMEOUT         10 /* msec */
31 #define I2C_PNX_SPEED_KHZ       100
32 #define I2C_PNX_REGION_SIZE     0x100
33
34 static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
35 {
36         while (timeout > 0 &&
37                         (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
38                 mdelay(1);
39                 timeout--;
40         }
41         return (timeout <= 0);
42 }
43
44 static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
45 {
46         while (timeout > 0 &&
47                         (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
48                 mdelay(1);
49                 timeout--;
50         }
51         return (timeout <= 0);
52 }
53
54 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
55 {
56         struct timer_list *timer = &alg_data->mif.timer;
57         unsigned long expires = msecs_to_jiffies(I2C_PNX_TIMEOUT);
58
59         if (expires <= 1)
60                 expires = 2;
61
62         del_timer_sync(timer);
63
64         dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
65                 jiffies, expires);
66
67         timer->expires = jiffies + expires;
68         timer->data = (unsigned long)alg_data;
69
70         add_timer(timer);
71 }
72
73 /**
74  * i2c_pnx_start - start a device
75  * @slave_addr:         slave address
76  * @adap:               pointer to adapter structure
77  *
78  * Generate a START signal in the desired mode.
79  */
80 static int i2c_pnx_start(unsigned char slave_addr,
81         struct i2c_pnx_algo_data *alg_data)
82 {
83         dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
84                 slave_addr, alg_data->mif.mode);
85
86         /* Check for 7 bit slave addresses only */
87         if (slave_addr & ~0x7f) {
88                 dev_err(&alg_data->adapter.dev,
89                         "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
90                         alg_data->adapter.name, slave_addr);
91                 return -EINVAL;
92         }
93
94         /* First, make sure bus is idle */
95         if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
96                 /* Somebody else is monopolizing the bus */
97                 dev_err(&alg_data->adapter.dev,
98                         "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
99                         alg_data->adapter.name, slave_addr,
100                         ioread32(I2C_REG_CTL(alg_data)),
101                         ioread32(I2C_REG_STS(alg_data)));
102                 return -EBUSY;
103         } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
104                 /* Sorry, we lost the bus */
105                 dev_err(&alg_data->adapter.dev,
106                         "%s: Arbitration failure. Slave addr = %02x\n",
107                         alg_data->adapter.name, slave_addr);
108                 return -EIO;
109         }
110
111         /*
112          * OK, I2C is enabled and we have the bus.
113          * Clear the current TDI and AFI status flags.
114          */
115         iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
116                   I2C_REG_STS(alg_data));
117
118         dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
119                 (slave_addr << 1) | start_bit | alg_data->mif.mode);
120
121         /* Write the slave address, START bit and R/W bit */
122         iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
123                   I2C_REG_TX(alg_data));
124
125         dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
126
127         return 0;
128 }
129
130 /**
131  * i2c_pnx_stop - stop a device
132  * @adap:               pointer to I2C adapter structure
133  *
134  * Generate a STOP signal to terminate the master transaction.
135  */
136 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
137 {
138         /* Only 1 msec max timeout due to interrupt context */
139         long timeout = 1000;
140
141         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
142                 __func__, ioread32(I2C_REG_STS(alg_data)));
143
144         /* Write a STOP bit to TX FIFO */
145         iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
146
147         /* Wait until the STOP is seen. */
148         while (timeout > 0 &&
149                (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
150                 /* may be called from interrupt context */
151                 udelay(1);
152                 timeout--;
153         }
154
155         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
156                 __func__, ioread32(I2C_REG_STS(alg_data)));
157 }
158
159 /**
160  * i2c_pnx_master_xmit - transmit data to slave
161  * @adap:               pointer to I2C adapter structure
162  *
163  * Sends one byte of data to the slave
164  */
165 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
166 {
167         u32 val;
168
169         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
170                 __func__, ioread32(I2C_REG_STS(alg_data)));
171
172         if (alg_data->mif.len > 0) {
173                 /* We still have something to talk about... */
174                 val = *alg_data->mif.buf++;
175
176                 if (alg_data->mif.len == 1)
177                         val |= stop_bit;
178
179                 alg_data->mif.len--;
180                 iowrite32(val, I2C_REG_TX(alg_data));
181
182                 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
183                         __func__, val, alg_data->mif.len + 1);
184
185                 if (alg_data->mif.len == 0) {
186                         if (alg_data->last) {
187                                 /* Wait until the STOP is seen. */
188                                 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
189                                         dev_err(&alg_data->adapter.dev,
190                                                 "The bus is still active after timeout\n");
191                         }
192                         /* Disable master interrupts */
193                         iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
194                                 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
195                                   I2C_REG_CTL(alg_data));
196
197                         del_timer_sync(&alg_data->mif.timer);
198
199                         dev_dbg(&alg_data->adapter.dev,
200                                 "%s(): Waking up xfer routine.\n",
201                                 __func__);
202
203                         complete(&alg_data->mif.complete);
204                 }
205         } else if (alg_data->mif.len == 0) {
206                 /* zero-sized transfer */
207                 i2c_pnx_stop(alg_data);
208
209                 /* Disable master interrupts. */
210                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
211                         ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
212                           I2C_REG_CTL(alg_data));
213
214                 /* Stop timer. */
215                 del_timer_sync(&alg_data->mif.timer);
216                 dev_dbg(&alg_data->adapter.dev,
217                         "%s(): Waking up xfer routine after zero-xfer.\n",
218                         __func__);
219
220                 complete(&alg_data->mif.complete);
221         }
222
223         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
224                 __func__, ioread32(I2C_REG_STS(alg_data)));
225
226         return 0;
227 }
228
229 /**
230  * i2c_pnx_master_rcv - receive data from slave
231  * @adap:               pointer to I2C adapter structure
232  *
233  * Reads one byte data from the slave
234  */
235 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
236 {
237         unsigned int val = 0;
238         u32 ctl = 0;
239
240         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
241                 __func__, ioread32(I2C_REG_STS(alg_data)));
242
243         /* Check, whether there is already data,
244          * or we didn't 'ask' for it yet.
245          */
246         if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
247                 dev_dbg(&alg_data->adapter.dev,
248                         "%s(): Write dummy data to fill Rx-fifo...\n",
249                         __func__);
250
251                 if (alg_data->mif.len == 1) {
252                         /* Last byte, do not acknowledge next rcv. */
253                         val |= stop_bit;
254
255                         /*
256                          * Enable interrupt RFDAIE (data in Rx fifo),
257                          * and disable DRMIE (need data for Tx)
258                          */
259                         ctl = ioread32(I2C_REG_CTL(alg_data));
260                         ctl |= mcntrl_rffie | mcntrl_daie;
261                         ctl &= ~mcntrl_drmie;
262                         iowrite32(ctl, I2C_REG_CTL(alg_data));
263                 }
264
265                 /*
266                  * Now we'll 'ask' for data:
267                  * For each byte we want to receive, we must
268                  * write a (dummy) byte to the Tx-FIFO.
269                  */
270                 iowrite32(val, I2C_REG_TX(alg_data));
271
272                 return 0;
273         }
274
275         /* Handle data. */
276         if (alg_data->mif.len > 0) {
277                 val = ioread32(I2C_REG_RX(alg_data));
278                 *alg_data->mif.buf++ = (u8) (val & 0xff);
279                 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
280                         __func__, val, alg_data->mif.len);
281
282                 alg_data->mif.len--;
283                 if (alg_data->mif.len == 0) {
284                         if (alg_data->last)
285                                 /* Wait until the STOP is seen. */
286                                 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
287                                         dev_err(&alg_data->adapter.dev,
288                                                 "The bus is still active after timeout\n");
289
290                         /* Disable master interrupts */
291                         ctl = ioread32(I2C_REG_CTL(alg_data));
292                         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
293                                  mcntrl_drmie | mcntrl_daie);
294                         iowrite32(ctl, I2C_REG_CTL(alg_data));
295
296                         /* Kill timer. */
297                         del_timer_sync(&alg_data->mif.timer);
298                         complete(&alg_data->mif.complete);
299                 }
300         }
301
302         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
303                 __func__, ioread32(I2C_REG_STS(alg_data)));
304
305         return 0;
306 }
307
308 /* SMBus receive handler, called from ISR */
309 static int i2c_pnx_smbus_rx(struct i2c_pnx_algo_data *smbus)
310 {
311         struct i2c_pnx_smbus *smb = &smbus->smb;
312         while (!(ioread32(I2C_REG_STS(smbus)) & mstatus_rfe)) {
313                 smb->rx_buf[smb->rx_cnt++] =
314                         (u8) ioread32(I2C_REG_RX(smbus));
315                 dev_dbg(&smbus->adapter.dev, "Rx Char: %02x\n",
316                                 smb->rx_buf[smb->rx_cnt - 1]);
317
318                 /* If Rx char is not length then continue receiving */
319                 if ((smb->rx_cnt != 1) ||
320                         !(smb->flags & I2C_PNX_SMBUS_BLOCK_RX))
321                         continue;
322
323                 /* If Received char is length, check for validity */
324                 if (unlikely(smb->rx_buf[0] <= 0 &&
325                         smb->rx_buf[0] > smb->max_rx_len)) {
326                         dev_dbg(&smbus->adapter.dev, "ERR: SMBus received "
327                                         "invalid transfer length %d from slave"
328                                         " %#02x during a block transfer.\n",
329                                         smb->rx_buf[0],
330                                         smb->slave_addr);
331                         smb->ret = -EIO;
332                         complete(&smb->complete);
333                         smb->flags |= I2C_PNX_SMBUS_NEED_RESET;
334                         return 1;
335                 }
336
337                 /* There is a hardware BUG, that makes receiving
338                  * only length not possible, so we receive length
339                  * and a byte of data, if that is the only byte to
340                  * be received the the transfer must stop right away
341                  **/
342                 if (smb->rx_buf[0] == 1) {
343                         /* Stop xfer right away */
344                         iowrite32(stop_bit, I2C_REG_TX(smbus));
345                         iowrite32(ioread32(I2C_REG_CTL(smbus)) &
346                                         ~(mcntrl_drmie | mcntrl_tffie),
347                                         I2C_REG_CTL(smbus));
348                         return 1;
349                 }
350
351                 dev_dbg(&smbus->adapter.dev, "Set Len:%d\n",
352                                 smb->rx_buf[0]);
353                 smb->len += smb->rx_buf[0] - 1;
354                 smb->tx_buf[smb->len - 1] |= stop_bit;
355                 iowrite32(ioread32(I2C_REG_CTL(smbus)) |
356                                   mcntrl_tffie, I2C_REG_CTL(smbus));
357         }
358         return 0;
359 }
360
361 /* SMBUs interrupt handler */
362 static irqreturn_t i2c_pnx_smbus_isr(int irq, void *dev_id)
363 {
364         struct i2c_pnx_algo_data *smbus = dev_id;
365         struct i2c_pnx_smbus *smb = &smbus->smb;
366         u32 stat, ctl;
367         stat = ioread32(I2C_REG_STS(smbus));
368         ctl = ioread32(I2C_REG_CTL(smbus));
369
370         dev_dbg(&smbus->adapter.dev, "ISR: stat = %#08x, "
371                         "ctrl = %#08x\r\n", stat, ctl);
372
373         /* Handle Rx data */
374         if (((stat & mstatus_rff) && (ctl & mcntrl_rffie)) ||
375             (!(stat & mstatus_rfe) && (ctl & mcntrl_daie))) {
376                 if (i2c_pnx_smbus_rx(smbus))
377                         return IRQ_HANDLED;
378                 stat = ioread32(I2C_REG_STS(smbus));
379                 ctl = ioread32(I2C_REG_CTL(smbus));
380         }
381
382         /* Handle Transmit */
383         if (((stat & mstatus_drmi) && (ctl & mcntrl_drmie)) ||
384             (!(stat & mstatus_rff) && (ctl & mcntrl_tffie))) {
385
386                 /* Push data into FIFO until we run out of data
387                  * or TX/RX fifo is full
388                  **/
389                 for (; (smb->index < smb->len) &&
390                      !(ioread32(I2C_REG_STS(smbus)) &
391                                  (mstatus_tff | mstatus_rff));
392                      smb->index++) {
393                         iowrite32(smb->tx_buf[smb->index], I2C_REG_TX(smbus));
394                         dev_dbg(&smbus->adapter.dev, "Tx Char: %03x\n",
395                                         smb->tx_buf[smb->index]);
396                 }
397
398                 /* Stop further transmit if we run out of data */
399                 if (smb->index >= smb->len) {
400                         iowrite32(ctl & ~(mcntrl_drmie | mcntrl_tffie),
401                                         I2C_REG_CTL(smbus));
402                 }
403                 return IRQ_HANDLED;
404         }
405
406         /* Handle Arbitration loss */
407         if (unlikely((stat & mstatus_afi) && (ctl & mcntrl_afie))) {
408                 dev_dbg(&smbus->adapter.dev, "Aribitration lost during"
409                                 " transfer to/from slave addr %02x\r\n",
410                                 smb->slave_addr);
411                 smb->ret = -EAGAIN;
412                 complete(&smb->complete);
413                 smb->flags |= I2C_PNX_SMBUS_NEED_RESET;
414                 /* We are done! */
415                 iowrite32(0, I2C_REG_CTL(smbus));
416                 return IRQ_HANDLED;
417         }
418
419         /* Handle NACK reception */
420         if (unlikely((stat & mstatus_nai) && (ctl & mcntrl_naie))) {
421                 dev_dbg(&smbus->adapter.dev, "Nack received!\n");
422                 smb->ret = -EIO;
423                 complete(&smb->complete);
424                 smb->flags |= I2C_PNX_SMBUS_NEED_RESET;
425                 /* We are done! */
426                 iowrite32(0, I2C_REG_CTL(smbus));
427                 return IRQ_HANDLED;
428         }
429
430         /* Handle Xfer Done */
431         if ((stat & mstatus_tdi) &&
432             (mcntrl_tdie & ctl)) {
433                 dev_dbg(&smbus->adapter.dev, "SMBus Xfer Done!\r\n");
434                 /* Transmission is done */
435                 smb->ret = 0;
436                 complete(&smb->complete);
437                 iowrite32(mstatus_tdi, I2C_REG_STS(smbus));
438                 iowrite32(0, I2C_REG_CTL(smbus));
439                 return IRQ_HANDLED;
440         }
441
442         return IRQ_HANDLED;
443 }
444
445 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
446 {
447         struct i2c_pnx_algo_data *alg_data = dev_id;
448         u32 stat, ctl;
449
450         /* If it is an SMBUS xfer let another handler do the task */
451         if (alg_data->smb.flags & I2C_PNX_SMBUS_ACTIVE)
452                 return i2c_pnx_smbus_isr(irq, dev_id);
453
454         dev_dbg(&alg_data->adapter.dev,
455                 "%s(): mstat = %x mctrl = %x, mode = %d\n",
456                 __func__,
457                 ioread32(I2C_REG_STS(alg_data)),
458                 ioread32(I2C_REG_CTL(alg_data)),
459                 alg_data->mif.mode);
460         stat = ioread32(I2C_REG_STS(alg_data));
461
462         /* let's see what kind of event this is */
463         if (stat & mstatus_afi) {
464                 /* We lost arbitration in the midst of a transfer */
465                 alg_data->mif.ret = -EIO;
466
467                 /* Disable master interrupts. */
468                 ctl = ioread32(I2C_REG_CTL(alg_data));
469                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
470                          mcntrl_drmie);
471                 iowrite32(ctl, I2C_REG_CTL(alg_data));
472
473                 /* Stop timer, to prevent timeout. */
474                 del_timer_sync(&alg_data->mif.timer);
475                 complete(&alg_data->mif.complete);
476         } else if (stat & mstatus_nai) {
477                 /* Slave did not acknowledge, generate a STOP */
478                 dev_dbg(&alg_data->adapter.dev,
479                         "%s(): Slave did not acknowledge, generating a STOP.\n",
480                         __func__);
481                 i2c_pnx_stop(alg_data);
482
483                 /* Disable master interrupts. */
484                 ctl = ioread32(I2C_REG_CTL(alg_data));
485                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
486                          mcntrl_drmie);
487                 iowrite32(ctl, I2C_REG_CTL(alg_data));
488
489                 /* Our return value. */
490                 alg_data->mif.ret = -EIO;
491
492                 /* Stop timer, to prevent timeout. */
493                 del_timer_sync(&alg_data->mif.timer);
494                 complete(&alg_data->mif.complete);
495         } else {
496                 /*
497                  * Two options:
498                  * - Master Tx needs data.
499                  * - There is data in the Rx-fifo
500                  * The latter is only the case if we have requested for data,
501                  * via a dummy write. (See 'i2c_pnx_master_rcv'.)
502                  * We therefore check, as a sanity check, whether that interrupt
503                  * has been enabled.
504                  */
505                 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
506                         if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
507                                 i2c_pnx_master_xmit(alg_data);
508                         } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
509                                 i2c_pnx_master_rcv(alg_data);
510                         }
511                 }
512         }
513
514         /* Clear TDI and AFI bits */
515         stat = ioread32(I2C_REG_STS(alg_data));
516         iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
517
518         dev_dbg(&alg_data->adapter.dev,
519                 "%s(): exiting, stat = %x ctrl = %x.\n",
520                  __func__, ioread32(I2C_REG_STS(alg_data)),
521                  ioread32(I2C_REG_CTL(alg_data)));
522
523         return IRQ_HANDLED;
524 }
525
526 static void i2c_pnx_timeout(unsigned long data)
527 {
528         struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data;
529         u32 ctl;
530
531         dev_err(&alg_data->adapter.dev,
532                 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
533                 ioread32(I2C_REG_STS(alg_data)),
534                 ioread32(I2C_REG_CTL(alg_data)));
535
536         /* Reset master and disable interrupts */
537         ctl = ioread32(I2C_REG_CTL(alg_data));
538         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
539         iowrite32(ctl, I2C_REG_CTL(alg_data));
540
541         ctl |= mcntrl_reset;
542         iowrite32(ctl, I2C_REG_CTL(alg_data));
543         wait_reset(I2C_PNX_TIMEOUT, alg_data);
544         alg_data->mif.ret = -EIO;
545         complete(&alg_data->mif.complete);
546 }
547
548 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
549 {
550         u32 stat;
551
552         if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
553                 dev_err(&alg_data->adapter.dev,
554                         "%s: Bus is still active after xfer. Reset it...\n",
555                         alg_data->adapter.name);
556                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
557                           I2C_REG_CTL(alg_data));
558                 wait_reset(I2C_PNX_TIMEOUT, alg_data);
559         } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
560                 /* If there is data in the fifo's after transfer,
561                  * flush fifo's by reset.
562                  */
563                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
564                           I2C_REG_CTL(alg_data));
565                 wait_reset(I2C_PNX_TIMEOUT, alg_data);
566         } else if (stat & mstatus_nai) {
567                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
568                           I2C_REG_CTL(alg_data));
569                 wait_reset(I2C_PNX_TIMEOUT, alg_data);
570         }
571 }
572
573 /**
574  * i2c_pnx_xfer - I2C Protocol Transfer routine
575  * @adap:               pointer to I2C adapter structure
576  * @msgs:               array of messages
577  * @num:                number of messages
578  *
579  * Initiates the transfer
580  */
581 static int
582 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
583 {
584         struct i2c_msg *pmsg;
585         int rc = 0, completed = 0, i;
586         struct i2c_pnx_algo_data *alg_data = adap->algo_data;
587         u32 stat;
588
589         clk_enable(alg_data->clk);
590
591         stat = ioread32(I2C_REG_STS(alg_data));
592
593         dev_dbg(&alg_data->adapter.dev,
594                 "%s(): entering: %d messages, stat = %04x.\n",
595                 __func__, num, stat);
596
597         bus_reset_if_active(alg_data);
598
599         /* Process transactions in a loop. */
600         for (i = 0; rc >= 0 && i < num; i++) {
601                 u8 addr;
602
603                 pmsg = &msgs[i];
604                 addr = pmsg->addr;
605
606                 if (pmsg->flags & I2C_M_TEN) {
607                         dev_err(&alg_data->adapter.dev,
608                                 "%s: 10 bits addr not supported!\n",
609                                 alg_data->adapter.name);
610                         rc = -EINVAL;
611                         clk_disable(alg_data->clk);
612                         break;
613                 }
614
615                 alg_data->mif.buf = pmsg->buf;
616                 alg_data->mif.len = pmsg->len;
617                 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
618                         I2C_SMBUS_READ : I2C_SMBUS_WRITE;
619                 alg_data->mif.ret = 0;
620                 alg_data->last = (i == num - 1);
621
622                 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
623                         __func__, alg_data->mif.mode, alg_data->mif.len);
624
625                 i2c_pnx_arm_timer(alg_data);
626
627                 /* initialize the completion var */
628                 init_completion(&alg_data->mif.complete);
629
630                 /* Enable master interrupt */
631                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
632                                 mcntrl_naie | mcntrl_drmie,
633                           I2C_REG_CTL(alg_data));
634
635                 /* Put start-code and slave-address on the bus. */
636                 rc = i2c_pnx_start(addr, alg_data);
637                 if (rc < 0)
638                         break;
639
640                 /* Wait for completion */
641                 wait_for_completion(&alg_data->mif.complete);
642
643                 if (!(rc = alg_data->mif.ret))
644                         completed++;
645                 dev_dbg(&alg_data->adapter.dev,
646                         "%s(): Complete, return code = %d.\n",
647                         __func__, rc);
648
649                 /* Clear TDI and AFI bits in case they are set. */
650                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
651                         dev_dbg(&alg_data->adapter.dev,
652                                 "%s: TDI still set... clearing now.\n",
653                                 alg_data->adapter.name);
654                         iowrite32(stat, I2C_REG_STS(alg_data));
655                 }
656                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
657                         dev_dbg(&alg_data->adapter.dev,
658                                 "%s: AFI still set... clearing now.\n",
659                                 alg_data->adapter.name);
660                         iowrite32(stat, I2C_REG_STS(alg_data));
661                 }
662         }
663
664         bus_reset_if_active(alg_data);
665
666         /* Cleanup to be sure... */
667         alg_data->mif.buf = NULL;
668         alg_data->mif.len = 0;
669
670         dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
671                 __func__, ioread32(I2C_REG_STS(alg_data)));
672
673         clk_disable(alg_data->clk);
674
675         if (completed != num)
676                 return ((rc < 0) ? rc : -EREMOTEIO);
677
678         return num;
679 }
680
681 /* Checks for the state of I2C BUS */
682 static int i2c_pnx_smbus_check(struct i2c_pnx_algo_data *smbus)
683 {
684         u32 stat;
685         int need_reset;
686
687         stat = ioread32(I2C_REG_STS(smbus));
688
689         /* Reset if bus is still active or a NACK from prev xfer pending */
690         need_reset = stat & (mstatus_active | mstatus_nai);
691
692         /* Reset if TXFIFO or RXFIFO is not empty */
693         need_reset |= ~stat & (mstatus_rfe | mstatus_tfe);
694
695         if (unlikely(need_reset)) {
696                 dev_dbg(&smbus->adapter.dev, "SMBus is not in idle state"
697                                 " before transfer, resetting it...\r\n");
698                 iowrite32(ioread32(I2C_REG_CTL(smbus)) | mcntrl_reset,
699                           I2C_REG_CTL(smbus));
700                 wait_reset(I2C_PNX_TIMEOUT, smbus);
701         }
702
703         stat = ioread32(I2C_REG_STS(smbus));
704
705         /* if the bus is still busy ask i2c-core to retry after sometime */
706         if (stat & mstatus_active) {
707                 dev_dbg(&smbus->adapter.dev, "SMBus is still active!\r\n");
708                 return -EAGAIN;
709         }
710
711         return 0;
712 }
713
714 /* Initialize SMBus structure */
715 static void i2c_pnx_smbus_init(struct i2c_pnx_algo_data *smbus)
716 {
717         struct i2c_pnx_smbus *smb = &smbus->smb;
718         smb->index = 0;
719         smb->ret = 0;
720         smb->flags = I2C_PNX_SMBUS_ACTIVE;
721         smb->len = 0;
722         smb->rx_cnt = 0;
723         iowrite32(mstatus_tdi, I2C_REG_STS(smbus));
724         init_completion(&smb->complete);
725 }
726
727 static void i2c_pnx_fill_buffer(u16 *to, u8 *from, int cnt)
728 {
729         int i;
730         for (i = 0; i < cnt; i++)
731                 to[i] = from ? from[i] : 0;
732 }
733
734 /**
735  * i2c_pnx_smbus_xfer - SMBUS protocol transfer routine
736  * @adapter:    pointer to I2C adapter structure
737  * @msgs:               array of messages
738  * @num:                number of messages
739  *
740  * Initiates the transfer
741  */
742 static int i2c_pnx_smbus_xfer(struct i2c_adapter *adapter,
743                 u16 addr, unsigned short flags, char read_write, u8 command,
744                 int size, union i2c_smbus_data *data)
745 {
746         struct i2c_pnx_algo_data *smbus = adapter->algo_data;
747         struct i2c_pnx_smbus *smb = &smbus->smb;
748         u16 *tx_buf = smb->tx_buf;
749         int read_flag, err;
750         int len = 0, i = 0;
751
752         dev_dbg(&adapter->dev, "SMBus xfer request: Slave addr %#02x,"
753                         "command=%d, operation=%d\r\n", addr, command, size);
754
755         smb->slave_addr = addr;
756         /* All our ops take 8-bit shifted addresses */
757         addr <<= 1;
758         read_flag = read_write == I2C_SMBUS_READ;
759
760         clk_enable(smbus->clk);
761
762         err = i2c_pnx_smbus_check(smbus);
763         if (unlikely(err)) {
764                 clk_disable(smbus->clk);
765                 return err;
766         }
767
768         i2c_pnx_smbus_init(smbus);
769
770         smb->rx_buf = data->block;
771         switch (size) {
772         case I2C_SMBUS_QUICK:
773                 tx_buf[0] = addr | start_bit | stop_bit | read_flag;
774                 read_flag = 0;
775                 smb->len = 1;
776                 break;
777
778         case I2C_SMBUS_BYTE:
779                 tx_buf[0] = addr | start_bit | read_flag;
780                 tx_buf[1] = command | stop_bit;
781                 smb->len = 2;
782                 break;
783
784         case I2C_SMBUS_BYTE_DATA:
785                 i = 0;
786                 tx_buf[i++] = addr | start_bit;
787                 tx_buf[i++] = command;
788                 if (read_flag)
789                         tx_buf[i++] = addr | start_bit | 1;
790                 tx_buf[i++] = data->byte | stop_bit;
791                 smb->len = i;
792                 break;
793
794         case I2C_SMBUS_WORD_DATA:
795                 i = 0;
796                 tx_buf[i++] = addr | start_bit;
797                 tx_buf[i++] = command;
798                 if (read_flag)
799                         tx_buf[i++] = addr | start_bit | 1;
800                 tx_buf[i++] = (data->word & 0xFF); /* Low Word */
801                 tx_buf[i++] = ((data->word >> 8) & 0xFF) | stop_bit;
802                 smb->len = i;
803                 smb->flags |= I2C_PNX_SMBUS_WORD_RX;
804                 break;
805
806         case I2C_SMBUS_BLOCK_DATA:
807                 len = data->block[0];
808                 tx_buf[i++] = addr | start_bit;
809                 tx_buf[i++] = command;
810                 if (read_flag) {
811                         tx_buf[i++] = addr | start_bit | 1;
812                         i2c_pnx_fill_buffer(&tx_buf[i],
813                                         (u8 *)NULL, I2C_SMBUS_BLOCK_MAX + 1);
814                         tx_buf[I2C_SMBUS_BLOCK_MAX + i] |= stop_bit;
815                         smb->rx_buf = data->block;
816                         smb->flags |= I2C_PNX_SMBUS_BLOCK_RX;
817                         smb->len = i + 2;
818                         smb->max_rx_len = I2C_SMBUS_BLOCK_MAX;
819                 } else {
820                         if (!len) {
821                                 clk_disable(smbus->clk);
822                                 return -EIO;
823                         }
824                         i2c_pnx_fill_buffer(&tx_buf[i],
825                             data->block, len + 1);
826                         tx_buf[len + i] |= stop_bit;
827                         smb->len = len + i + 1;
828                 }
829                 break;
830
831         case I2C_SMBUS_PROC_CALL:
832                 tx_buf[0] = addr | start_bit;
833                 tx_buf[1] = command;
834                 tx_buf[2] = data->word & 0xFF;
835                 tx_buf[3] = (data->word >> 8) & 0xFF;
836                 tx_buf[4] = addr | start_bit | 1;
837                 tx_buf[5] = 0;
838                 tx_buf[6] = 0 | stop_bit;
839                 smb->len = 7;
840                 smb->max_rx_len = 2;
841                 smb->flags |= I2C_PNX_SMBUS_WORD_RX;
842                 read_flag = 1;
843                 break;
844
845         case I2C_SMBUS_BLOCK_PROC_CALL:
846                 len = data->block[0];
847                 if (!len) {
848                         clk_disable(smbus->clk);
849                         return -EINVAL;
850                 }
851                 tx_buf[0] = addr | start_bit;
852                 tx_buf[1] = command;
853                 i2c_pnx_fill_buffer(&tx_buf[2],
854                         data->block, len + 1);
855                 i = 3 + len;
856                 tx_buf[i++] = addr | start_bit | 1;
857                 len = I2C_SMBUS_BLOCK_MAX - len;
858                 i2c_pnx_fill_buffer(&tx_buf[i],
859                     NULL, len + 1);
860                 tx_buf[i+len] = stop_bit;
861                 smb->flags |= I2C_PNX_SMBUS_BLOCK_RX;
862                 smb->max_rx_len = len;
863                 smb->len = 2 + i;
864                 read_flag = 1;
865                 break;
866
867         default:
868                 dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
869                 clk_disable(smbus->clk);
870                 return -EINVAL;
871         }
872         /* Enable interrupts and wait for completion of xfer */
873         iowrite32(ioread32(I2C_REG_CTL(smbus)) | 0xEF, I2C_REG_CTL(smbus));
874
875         err = wait_for_completion_interruptible_timeout(&smb->complete, HZ);
876
877         /* Disable interrupts */
878         iowrite32(ioread32(I2C_REG_CTL(smbus)) & ~0xEF, I2C_REG_CTL(smbus));
879         smb->flags &= ~I2C_PNX_SMBUS_ACTIVE;
880
881         if (err == 0) { /* Xfer timedout */
882                 dev_dbg(&adapter->dev, "SMBus Xfer timedout"
883                                 "[Slave Addr: %02x]\n", addr >> 1);
884                 err = -ETIMEDOUT;
885                 smb->flags |= I2C_PNX_SMBUS_NEED_RESET;
886         } else if (err > 0) { /* No error */
887                 err = smb->ret;
888         } else { /* < 0 Possibly interrupted */
889                 smb->flags |= I2C_PNX_SMBUS_NEED_RESET;
890         }
891
892         /* Handle post processing for a Rx xfer */
893         if (!err && read_flag) {
894                 len = (smb->flags & I2C_PNX_SMBUS_BLOCK_RX) ?
895                         data->block[0] + 1 : 1;
896
897                 if (smb->flags & I2C_PNX_SMBUS_WORD_RX) {
898                         len = 2;
899                         /* Return endian independent data */
900                         data->word = (data->block[0] & 0xFF) |
901                                 ((data->block[1] & 0xFF) << 8);
902                 }
903                 if (unlikely(len > smb->rx_cnt)) {
904                         dev_err(&adapter->dev, "SMBus: Rx count error "
905                                         "[Expected:%d, Got:%d] slave: %#02x\n",
906                                         len, smb->rx_cnt, addr >> 1);
907                         err = -EIO;
908                 }
909         }
910
911         if (unlikely(smb->flags & I2C_PNX_SMBUS_NEED_RESET)) {
912                 iowrite32(ioread32(I2C_REG_CTL(smbus)) | mcntrl_reset,
913                           I2C_REG_CTL(smbus));
914         }
915
916         clk_disable(smbus->clk);
917
918         return err;
919 }
920
921 /**
922  * i2c_pnx_func - SMBUS protocol transfer routine
923  * @adapt:      pointer to I2C adapter structure
924  *
925  * Provides the list of functionality provided by pnx-i2c
926  *
927  * I2C_FUNC_10BIT_ADDR - is supported by hardware but
928  * this driver does not implement it!
929  */
930 static u32 i2c_pnx_func(struct i2c_adapter *adap)
931 {
932         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
933                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
934                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
935                I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
936 }
937
938 static const struct i2c_algorithm pnx_algorithm = {
939         .master_xfer = i2c_pnx_xfer,
940         .smbus_xfer  = i2c_pnx_smbus_xfer,
941         .functionality = i2c_pnx_func,
942 };
943
944 static int __devinit i2c_pnx_probe(struct platform_device *pdev)
945 {
946         unsigned long tmp;
947         int ret = 0;
948         struct i2c_pnx_algo_data *alg_data;
949         unsigned long freq;
950         struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
951
952         if (!i2c_pnx || !i2c_pnx->name) {
953                 dev_err(&pdev->dev, "%s: no platform data supplied\n",
954                        __func__);
955                 ret = -EINVAL;
956                 goto out;
957         }
958
959         alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
960         if (!alg_data) {
961                 ret = -ENOMEM;
962                 goto err_kzalloc;
963         }
964
965         platform_set_drvdata(pdev, alg_data);
966
967         strlcpy(alg_data->adapter.name, i2c_pnx->name,
968                 sizeof(alg_data->adapter.name));
969         alg_data->adapter.dev.parent = &pdev->dev;
970         alg_data->adapter.algo = &pnx_algorithm;
971         alg_data->adapter.algo_data = alg_data;
972         alg_data->adapter.nr = pdev->id;
973         alg_data->i2c_pnx = i2c_pnx;
974
975         alg_data->clk = clk_get(&pdev->dev, NULL);
976         if (IS_ERR(alg_data->clk)) {
977                 ret = PTR_ERR(alg_data->clk);
978                 goto out_drvdata;
979         }
980
981         init_timer(&alg_data->mif.timer);
982         alg_data->mif.timer.function = i2c_pnx_timeout;
983         alg_data->mif.timer.data = (unsigned long)alg_data;
984
985         /* Register I/O resource */
986         if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE,
987                                 pdev->name)) {
988                 dev_err(&pdev->dev,
989                        "I/O region 0x%08x for I2C already in use.\n",
990                        i2c_pnx->base);
991                 ret = -ENODEV;
992                 goto out_clkget;
993         }
994
995         alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE);
996         if (!alg_data->ioaddr) {
997                 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
998                 ret = -ENOMEM;
999                 goto out_release;
1000         }
1001
1002         ret = clk_enable(alg_data->clk);
1003         if (ret)
1004                 goto out_unmap;
1005
1006         freq = clk_get_rate(alg_data->clk);
1007
1008         /*
1009          * Clock Divisor High This value is the number of system clocks
1010          * the serial clock (SCL) will be high.
1011          * For example, if the system clock period is 50 ns and the maximum
1012          * desired serial period is 10000 ns (100 kHz), then CLKHI would be
1013          * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
1014          * programmed into CLKHI will vary from this slightly due to
1015          * variations in the output pad's rise and fall times as well as
1016          * the deglitching filter length.
1017          */
1018
1019         tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
1020         if (tmp > 0x3FF)
1021                 tmp = 0x3FF;
1022         iowrite32(tmp, I2C_REG_CKH(alg_data));
1023         iowrite32(tmp, I2C_REG_CKL(alg_data));
1024
1025         iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
1026         if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
1027                 ret = -ENODEV;
1028                 goto out_clock;
1029         }
1030         init_completion(&alg_data->mif.complete);
1031
1032         ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt,
1033                         0, pdev->name, alg_data);
1034         if (ret)
1035                 goto out_clock;
1036
1037         /* Register this adapter with the I2C subsystem */
1038         ret = i2c_add_numbered_adapter(&alg_data->adapter);
1039         if (ret < 0) {
1040                 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
1041                 goto out_irq;
1042         }
1043
1044         dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
1045                alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq);
1046
1047         /* Disable clock until needed */
1048         clk_disable(alg_data->clk);
1049
1050         return 0;
1051
1052 out_irq:
1053         free_irq(i2c_pnx->irq, alg_data);
1054 out_clock:
1055         clk_disable(alg_data->clk);
1056 out_unmap:
1057         iounmap(alg_data->ioaddr);
1058 out_release:
1059         release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
1060 out_clkget:
1061         clk_put(alg_data->clk);
1062 out_drvdata:
1063         kfree(alg_data);
1064 err_kzalloc:
1065         platform_set_drvdata(pdev, NULL);
1066 out:
1067         return ret;
1068 }
1069
1070 static int __devexit i2c_pnx_remove(struct platform_device *pdev)
1071 {
1072         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
1073         struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx;
1074
1075         clk_enable(alg_data->clk);
1076         free_irq(i2c_pnx->irq, alg_data);
1077         i2c_del_adapter(&alg_data->adapter);
1078         clk_disable(alg_data->clk);
1079         iounmap(alg_data->ioaddr);
1080         release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
1081         clk_put(alg_data->clk);
1082         kfree(alg_data);
1083         platform_set_drvdata(pdev, NULL);
1084
1085         return 0;
1086 }
1087
1088 static struct platform_driver i2c_pnx_driver = {
1089         .driver = {
1090                 .name = "pnx-i2c",
1091                 .owner = THIS_MODULE,
1092         },
1093         .probe = i2c_pnx_probe,
1094         .remove = __devexit_p(i2c_pnx_remove),
1095 };
1096
1097 static int __init i2c_adap_pnx_init(void)
1098 {
1099         return platform_driver_register(&i2c_pnx_driver);
1100 }
1101
1102 static void __exit i2c_adap_pnx_exit(void)
1103 {
1104         platform_driver_unregister(&i2c_pnx_driver);
1105 }
1106
1107 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
1108 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
1109 MODULE_LICENSE("GPL");
1110 MODULE_ALIAS("platform:pnx-i2c");
1111
1112 /* We need to make sure I2C is initialized before USB */
1113 subsys_initcall(i2c_adap_pnx_init);
1114 module_exit(i2c_adap_pnx_exit);