arm: lpc32xx: Fix several system suspend related issues
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / suspend.S
1 /*
2  * arch/arm/mach-lpc32xx/suspend.S
3  *
4  * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
5  * Modified by Kevin Wells <kevin.wells@nxp.com>
6  *
7  * 2005 (c) MontaVista Software, Inc. This file is licensed under
8  * the terms of the GNU General Public License version 2. This program
9  * is licensed "as is" without any warranty of any kind, whether express
10  * or implied.
11  */
12 #include <linux/linkage.h>
13 #include <asm/assembler.h>
14 #include <mach/platform.h>
15 #include <mach/hardware.h>
16
17 /* Using named register defines makes the code easier to follow */
18 #define WORK1_REG                       r0
19 #define WORK2_REG                       r1
20 #define SAVED_HCLK_DIV_REG              r2
21 #define SAVED_HCLK_PLL_REG              r3
22 #define SAVED_DRAM_CLKCTRL_REG          r4
23 #define SAVED_PWR_CTRL_REG              r5
24 #define CLKPWRBASE_REG                  r6
25 #define EMCBASE_REG                     r7
26
27 #define LPC32XX_EMC_STATUS_OFFS         0x04
28 #define LPC32XX_EMC_STATUS_BUSY         0x1
29 #define LPC32XX_EMC_STATUS_SELF_RFSH    0x4
30
31 #define LPC32XX_CLKPWR_PWR_CTRL_OFFS    0x44
32 #define LPC32XX_CLKPWR_HCLK_DIV_OFFS    0x40
33 #define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
34
35 #define CLKPWR_PCLK_DIV_MASK1           0xFFFFFF83
36 #define CLKPWR_PCLK_DIV_MASK2           0xFFFFFE03
37
38         .text
39
40 ENTRY(lpc32xx_sys_suspend)
41         @ Save a copy of the used registers in IRAM, r0 is corrupted
42         adr     r0, tmp_stack_end
43         stmfd   r0!, {r3 - r7, sp, lr}
44
45         @ Load a few common register addresses
46         adr     WORK1_REG, reg_bases
47         ldr     CLKPWRBASE_REG, [WORK1_REG, #0]
48         ldr     EMCBASE_REG, [WORK1_REG, #4]
49
50         ldr     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
51                 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
52         orr     WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
53
54         @ Wait for SDRAM busy status to go busy and then idle
55         @ This guarantees a small windows where DRAM isn't busy
56 1:
57         ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
58         and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
59         cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
60         bne     1b @ Branch while idle
61 2:
62         ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
63         and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
64         cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
65         beq     2b @ Branch until idle
66
67         @ Setup self-refresh with support for manual exit of
68         @ self-refresh mode
69         str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
70         orr     WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
71         str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
72         str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
73
74         @ Wait for self-refresh acknowledge, clocks to the DRAM device
75         @ will automatically stop on start of self-refresh
76 3:
77         ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
78         and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
79         cmp     WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
80         bne     3b @ Branch until self-refresh mode starts
81
82         @ Set PCLK divider to 1 prior to direct-run mode entry
83         ldr     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
84                 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
85         and     WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK1
86         str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
87
88         @ Enter direct-run mode from run mode
89         bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
90         str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
91
92         @ Safe disable of DRAM clock in EMC block, prevents DDR sync
93         @ issues on restart
94         and     WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK2
95         str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
96
97         @ Save HCLK PLL state and disable HCLK PLL
98         ldr     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
99                 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
100         bic     WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
101         str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
102
103         @ Enter stop mode until an enabled event occurs
104         orr     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
105         str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
106
107         .rept 9
108         nop
109         .endr
110
111         @ Clear stop status now
112         bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
113         str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
114
115         @ Restore original HCLK PLL value and wait for PLL lock
116         str     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
117                 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
118 4:
119         ldr     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
120         ands WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
121         beq 4b
122
123         @ Re-enter run mode with self-refresh flag cleared, but no DRAM
124         @ update yet. DRAM is still in self-refresh
125         str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
126                 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
127
128         @ Restore original DRAM clock mode to restore DRAM clocks
129         str     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
130                 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
131
132         @ Clear self-refresh mode
133         orr     WORK1_REG, SAVED_PWR_CTRL_REG,\
134                 #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
135         str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
136         str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
137                 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
138
139         @ Wait for EMC to clear self-refresh mode
140 5:
141         ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
142         ands WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
143         bne 5b @ Branch until self-refresh has exited
144
145         @ restore regs and return
146         adr     r0, tmp_stack
147         ldmfd   r0!, {r3 - r7, sp, pc}
148
149 reg_bases:
150         .long   IO_ADDRESS(LPC32XX_CLK_PM_BASE)
151         .long   IO_ADDRESS(LPC32XX_EMC_BASE)
152
153 tmp_stack:
154         .long   0, 0, 0, 0, 0, 0, 0
155 tmp_stack_end:
156
157 ENTRY(lpc32xx_sys_suspend_sz)
158         .word   . - lpc32xx_sys_suspend