Initial 2.6.34 kernel release for the LPC32xx
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / phy3250.c
1 /*
2  * arch/arm/mach-lpc32xx/phy3250.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/sysdev.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/device.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/eeprom.h>
28 #include <linux/leds.h>
29 #include <linux/gpio.h>
30 #include <linux/input.h>
31 #include <linux/amba/bus.h>
32 #include <linux/amba/clcd.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/amba/mmci.h>
35 #include <sound/uda1380.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40
41 #include <mach/hardware.h>
42 #include <mach/platform.h>
43 #include <mach/board.h>
44 #include "common.h"
45
46 /*
47  * Mapped GPIOLIB GPIOs
48  */
49 #define SPI0_CS_GPIO            LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
50 #define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
51 #define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
52 #define LED_GPIO                LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
53 #define NAND_WP_GPIO            LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
54 #define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
55 #define MMC_STATUS_GPIO         LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
56
57 /*
58  * AMBA LCD controller
59  */
60 static struct clcd_panel conn_lcd_panel = {
61         .mode           = {
62                 .name           = "QVGA portrait",
63                 .refresh        = 60,
64                 .xres           = 240,
65                 .yres           = 320,
66                 .pixclock       = 191828,
67                 .left_margin    = 22,
68                 .right_margin   = 11,
69                 .upper_margin   = 2,
70                 .lower_margin   = 1,
71                 .hsync_len      = 5,
72                 .vsync_len      = 2,
73                 .sync           = 0,
74                 .vmode          = FB_VMODE_NONINTERLACED,
75         },
76         .width          = -1,
77         .height         = -1,
78         .tim2           = (TIM2_IVS | TIM2_IHS),
79         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
80                                 CNTL_LCDBPP16_565),
81         .bpp            = 16,
82 };
83 #define PANEL_SIZE (3 * SZ_64K)
84
85 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
86 {
87         dma_addr_t dma;
88
89         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
90                 PANEL_SIZE, &dma, GFP_KERNEL);
91         if (!fb->fb.screen_base) {
92                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
93                 return -ENOMEM;
94         }
95
96         fb->fb.fix.smem_start = dma;
97         fb->fb.fix.smem_len = PANEL_SIZE;
98         fb->panel = &conn_lcd_panel;
99
100         if (gpio_request(LCD_POWER_GPIO, "LCD power"))
101                 printk(KERN_ERR "Error requesting gpio %u",
102                         LCD_POWER_GPIO);
103         else if (gpio_direction_output(LCD_POWER_GPIO, 1))
104                 printk(KERN_ERR "Error setting gpio %u to output",
105                         LCD_POWER_GPIO);
106
107         if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
108                 printk(KERN_ERR "Error requesting gpio %u",
109                         BKL_POWER_GPIO);
110         else if (gpio_direction_output(BKL_POWER_GPIO, 1))
111                 printk(KERN_ERR "Error setting gpio %u to output",
112                         BKL_POWER_GPIO);
113
114         return 0;
115 }
116
117 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
118 {
119         return dma_mmap_writecombine(&fb->dev->dev, vma,
120                 fb->fb.screen_base, fb->fb.fix.smem_start,
121                 fb->fb.fix.smem_len);
122 }
123
124 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
125 {
126         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
127                 fb->fb.screen_base, fb->fb.fix.smem_start);
128 }
129
130 /*
131  * On some early LCD modules (1307.0), the backlight logic is inverted.
132  * For those board variants, swap the disable and enable states for
133  * BKL_POWER_GPIO.
134 */
135 static void clcd_disable(struct clcd_fb *fb)
136 {
137         gpio_set_value(BKL_POWER_GPIO, 0);
138         gpio_set_value(LCD_POWER_GPIO, 0);
139 }
140
141 static void clcd_enable(struct clcd_fb *fb)
142 {
143         gpio_set_value(BKL_POWER_GPIO, 1);
144         gpio_set_value(LCD_POWER_GPIO, 1);
145 }
146
147 static struct clcd_board lpc32xx_clcd_data = {
148         .name           = "Phytec LCD",
149         .check          = clcdfb_check,
150         .decode         = clcdfb_decode,
151         .disable        = clcd_disable,
152         .enable         = clcd_enable,
153         .setup          = lpc32xx_clcd_setup,
154         .mmap           = lpc32xx_clcd_mmap,
155         .remove         = lpc32xx_clcd_remove,
156 };
157
158 static struct amba_device lpc32xx_clcd_device = {
159         .dev                            = {
160                 .coherent_dma_mask      = ~0,
161                 .init_name              = "dev:clcd",
162                 .platform_data          = &lpc32xx_clcd_data,
163         },
164         .res                            = {
165                 .start                  = LPC32XX_LCD_BASE,
166                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
167                 .flags                  = IORESOURCE_MEM,
168         },
169         .dma_mask                       = ~0,
170         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
171 };
172
173 /*
174  * AMBA SSP (SPI)
175  */
176 static void phy3250_spi_cs_set(u32 control)
177 {
178         gpio_set_value(SPI0_CS_GPIO, (int) control);
179 }
180
181 static struct pl022_config_chip spi0_chip_info = {
182         .lbm                    = LOOPBACK_DISABLED,
183         .com_mode               = INTERRUPT_TRANSFER,
184         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
185         .hierarchy              = SSP_MASTER,
186         .slave_tx_disable       = 0,
187         .endian_tx              = SSP_TX_LSB,
188         .endian_rx              = SSP_RX_LSB,
189         .data_size              = SSP_DATA_BITS_8,
190         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
191         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
192         .clk_phase              = SSP_CLK_FIRST_EDGE,
193         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
194         .ctrl_len               = SSP_BITS_8,
195         .wait_state             = SSP_MWIRE_WAIT_ZERO,
196         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
197         .cs_control             = phy3250_spi_cs_set,
198 };
199
200 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
201         .bus_id                 = 0,
202         .num_chipselect         = 1,
203         .enable_dma             = 0,
204 };
205
206 static struct amba_device lpc32xx_ssp0_device = {
207         .dev                            = {
208                 .coherent_dma_mask      = ~0,
209                 .init_name              = "dev:ssp0",
210                 .platform_data          = &lpc32xx_ssp0_data,
211         },
212         .res                            = {
213                 .start                  = LPC32XX_SSP0_BASE,
214                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
215                 .flags                  = IORESOURCE_MEM,
216         },
217         .dma_mask                       = ~0,
218         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
219 };
220
221 /* AT25 driver registration */
222 static int __init phy3250_spi_board_register(void)
223 {
224 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
225         static struct spi_board_info info[] = {
226                 {
227                         .modalias = "spidev",
228                         .max_speed_hz = 5000000,
229                         .bus_num = 0,
230                         .chip_select = 0,
231                         .controller_data = &spi0_chip_info,
232                 },
233         };
234
235 #else
236         static struct spi_eeprom eeprom = {
237                 .name = "at25256a",
238                 .byte_len = 0x8000,
239                 .page_size = 64,
240                 .flags = EE_ADDR2,
241         };
242
243         static struct spi_board_info info[] = {
244                 {
245                         .modalias = "at25",
246                         .max_speed_hz = 5000000,
247                         .bus_num = 0,
248                         .chip_select = 0,
249                         .platform_data = &eeprom,
250                         .controller_data = &spi0_chip_info,
251                 },
252         };
253 #endif
254         return spi_register_board_info(info, ARRAY_SIZE(info));
255 }
256 arch_initcall(phy3250_spi_board_register);
257
258 /*
259  * Platform Data for UDA1380 Audiocodec.
260  * As there are no GPIOs for codec power & reset pins,
261  * dummy GPIO numbers are used.
262  */
263 static struct uda1380_platform_data uda1380_info = {
264         .gpio_power = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,10),
265         .gpio_reset = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,2),
266         .dac_clk    = UDA1380_DAC_CLK_WSPLL,
267 };
268
269 static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
270         {
271                 I2C_BOARD_INFO("pcf8563", 0x51),
272         },
273         {
274                 I2C_BOARD_INFO("uda1380", 0x18),
275                 .platform_data = &uda1380_info,
276         },
277 };
278
279 static struct gpio_led phy_leds[] = {
280         {
281                 .name                   = "led0",
282                 .gpio                   = LED_GPIO,
283                 .active_low             = 1,
284                 .default_trigger        = "heartbeat",
285         },
286 };
287
288 static struct gpio_led_platform_data led_data = {
289         .leds = phy_leds,
290         .num_leds = ARRAY_SIZE(phy_leds),
291 };
292
293 static struct platform_device lpc32xx_gpio_led_device = {
294         .name                   = "leds-gpio",
295         .id                     = -1,
296         .dev.platform_data      = &led_data,
297 };
298
299 /*
300  * Board specific key scanner driver data
301  */
302 #define PHY3250_KMATRIX_SIZE 1
303 static int lpc32xx_keymaps[] = {
304         KEY_1,  /* 1, 1 */
305 };
306
307 static struct lpc32XX_kscan_cfg lpc32xx_kscancfg = {
308         .matrix_sz      = PHY3250_KMATRIX_SIZE,
309         .keymap         = lpc32xx_keymaps,
310         /* About a 30Hz scan rate based on a 32KHz clock */
311         .deb_clks       = 3,
312         .scan_delay     = 34,
313 };
314
315 static struct resource kscan_resources[] = {
316         [0] = {
317                 .start  = LPC32XX_KSCAN_BASE,
318                 .end    = LPC32XX_KSCAN_BASE + SZ_4K - 1,
319                 .flags  = IORESOURCE_MEM,
320         },
321         [1] = {
322                 .start  = IRQ_LPC32XX_KEY,
323                 .end    = IRQ_LPC32XX_KEY,
324                 .flags  = IORESOURCE_IRQ,
325         },
326
327 };
328
329 static struct platform_device lpc32xx_kscan_device = {
330         .name           = "lpc32xx_keys",
331         .id             = 0,
332         .dev            = {
333                 .platform_data  = &lpc32xx_kscancfg,
334         },
335         .num_resources  = ARRAY_SIZE(kscan_resources),
336         .resource       = kscan_resources,
337 };
338
339 #if defined (CONFIG_MMC_ARMMMCI)
340 /*
341  * Returns 0 when card is removed, !0 when installed
342  */
343 unsigned int mmc_status(struct device *dev)
344 {
345         return gpio_get_value(MMC_STATUS_GPIO) & 1;
346 }
347
348 /*
349  * Enable or disable SD slot power
350  */
351 void mmc_power_enable(int enable)
352 {
353         if (enable != 0)
354                 gpio_set_value(MMC_PWR_ENABLE_GPIO,1);
355         else
356                 gpio_set_value(MMC_PWR_ENABLE_GPIO,0);
357 }
358
359 /*
360  * Board specific MMC driver data
361  */
362 struct mmci_platform_data lpc32xx_plat_data = {
363         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
364         .status         = mmc_status,
365         .capabilities   = MMC_CAP_4_BIT_DATA,
366         .gpio_wp        = -1,
367         .gpio_cd        = -1,
368 };
369
370 /*
371  * SD card controller resources
372  */
373 struct amba_device lpc32xx_mmc_device = {
374         .dev                            = {
375                 .coherent_dma_mask      = ~0,
376                 .init_name                 = "dev:mmc0",
377                 .platform_data          = &lpc32xx_plat_data,
378         },
379         .res                            = {
380                 .start                  = LPC32XX_SD_BASE,
381                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
382                 .flags                  = IORESOURCE_MEM,
383         },
384         .dma_mask                       = ~0,
385         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
386 };
387 #endif
388
389
390 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
391 /*
392  * Board specific NAND setup data
393  */
394 static int nandwp_enable(int enable)
395 {
396         if (enable != 0)
397                 gpio_set_value(NAND_WP_GPIO,0);
398         else 
399                 gpio_set_value(NAND_WP_GPIO,1);
400
401         return 1;
402 }
403 #define BLK_SIZE (512 * 32)
404 static struct mtd_partition __initdata phy3250_nand_partition[] = {
405         {
406                 .name   = "phy3250-boot",
407                 .offset = 0,
408                 .size   = (BLK_SIZE * 90)
409         },
410         {
411                 .name   = "phy3250-ubt-prms",
412                 .offset = MTDPART_OFS_APPEND,
413                 .size   = (BLK_SIZE * 10)
414         },
415         {
416                 .name   = "phy3250-kernel",
417                 .offset = MTDPART_OFS_APPEND,
418                 .size   = (BLK_SIZE * 256)
419         },
420         {
421                 .name   = "phy3250-rootfs",
422                 .offset = MTDPART_OFS_APPEND,
423                 .size   = MTDPART_SIZ_FULL
424         },
425 };
426 static struct mtd_partition * __init phy3250_nand_partitions(int size, int *num_partitions)
427 {
428         *num_partitions = ARRAY_SIZE(phy3250_nand_partition);
429         return phy3250_nand_partition;
430 }
431 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
432 {
433         .wdr_clks               = 3,
434         .wwidth                 = 28571428,
435         .whold                  = 100000000,
436         .wsetup                 = 66666666,
437         .rdr_clks               = 3,
438         .rwidth                 = 28571428,
439         .rhold                  = 100000000,
440         .rsetup                 = 66666666,
441         .use16bus               = 0,
442         .enable_write_prot      = nandwp_enable,
443         .partition_info         = phy3250_nand_partitions,
444 };
445
446 /*
447  * SLC NAND resources
448  */
449 static struct resource slc_nand_resources[] = {
450         [0] = {
451                 .start  = LPC32XX_SLC_BASE,
452                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
453                 .flags  = IORESOURCE_MEM,
454         },
455
456         [1] = {
457                 .start  = IRQ_LPC32XX_FLASH,
458                 .end    = IRQ_LPC32XX_FLASH,
459                 .flags  = IORESOURCE_IRQ,
460         },
461
462 };
463 static struct platform_device lpc32xx_slc_nand_device = {
464         .name           = "lpc32xx-nand",
465         .id             = 0,
466         .dev            = {
467                                 .platform_data  = &lpc32xx_nandcfg,
468         },
469         .num_resources  = ARRAY_SIZE(slc_nand_resources),
470         .resource       = slc_nand_resources,
471 };
472 #endif
473
474 /*
475  * Network Support
476  */
477 static struct lpc_net_cfg lpc32xx_netdata =
478 {
479         .phy_irq        = -1,
480         .phy_mask       = 0xFFFFFFF0,
481 };
482
483 static struct resource net_resources[] = {
484         [0] = {
485                 .start  = LPC32XX_ETHERNET_BASE,
486                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
487                 .flags  = IORESOURCE_MEM,
488         },
489
490         [1] = {
491                 .start  = IRQ_LPC32XX_ETHERNET,
492                 .end    = IRQ_LPC32XX_ETHERNET,
493                 .flags  = IORESOURCE_IRQ,
494         },
495
496 };
497
498 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
499 static struct platform_device lpc32xx_net_device = {
500         .name           = "lpc-net",
501         .id             = 0,
502         .dev            = {
503                 .dma_mask = &lpc32xx_mac_dma_mask,
504                 .coherent_dma_mask = 0xffffffffUL,
505                 .platform_data  = &lpc32xx_netdata,
506         },
507         .num_resources  = ARRAY_SIZE(net_resources),
508         .resource       = net_resources,
509 };
510
511 static struct platform_device *phy3250_devs[] __initdata = {
512         &lpc32xx_i2c0_device,
513         &lpc32xx_i2c1_device,
514         &lpc32xx_i2c2_device,
515         &lpc32xx_watchdog_device,
516         &lpc32xx_gpio_led_device,
517         &lpc32xx_rtc_device,
518         &lpc32xx_tsc_device,
519         &lpc32xx_kscan_device,
520         &lpc32xx_net_device,
521 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
522         &lpc32xx_slc_nand_device,
523 #endif
524 #if defined(CONFIG_USB_OHCI_HCD)
525         &lpc32xx_ohci_device,
526 #endif
527 #if defined(CONFIG_USB_GADGET_LPC32XX)
528         &lpc32xx_usbd_device,
529 #endif
530 };
531
532 static struct amba_device *amba_devs[] __initdata = {
533         &lpc32xx_clcd_device,
534         &lpc32xx_ssp0_device,
535 #if defined(CONFIG_MMC_ARMMMCI)
536         &lpc32xx_mmc_device,
537 #endif
538 };
539
540 /*
541  * Board specific functions
542  */
543 static void __init phy3250_board_init(void)
544 {
545         u32 tmp;
546         int i;
547
548         lpc32xx_gpio_init();
549
550         /* Register GPIOs used on this board */
551         if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
552                 printk(KERN_ERR "Error requesting gpio %u",
553                                 SPI0_CS_GPIO);
554         else if (gpio_direction_output(SPI0_CS_GPIO, 1))
555                 printk(KERN_ERR "Error setting gpio %u to output",
556                                 SPI0_CS_GPIO);
557
558 #if defined (CONFIG_MMC_ARMMMCI)
559         /* Enable SD slot power */
560         mmc_power_enable(1);
561 #endif
562
563         /* Setup network interface for RMII mode */
564         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
565         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
566         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
567         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
568
569         /* Setup SLC NAND controller muxing */
570         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
571                 LPC32XX_CLKPWR_NAND_CLK_CTRL);
572
573         /* Setup LCD muxing to RGB565 */
574         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
575                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
576                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
577         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
578         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
579
580         /* Set up I2C pull levels */
581         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
582         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
583                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
584         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
585
586         /* Disable IrDA pulsing support on UART6 */
587         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
588         tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
589         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
590
591         /* Enable DMA for I2S1 channel */
592         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
593         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
594         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
595
596         lpc32xx_serial_init();
597
598         /*
599          * AMBA peripheral clocks need to be enabled prior to AMBA device
600          * detection or a data fault will occur, so enable the clocks
601          * here. However, we don't want to enable them if the peripheral
602          * isn't included in the image
603          */
604 #if defined(CONFIG_MMC_ARMMMCI)
605         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
606         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
607         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
608 #endif
609
610 #ifdef CONFIG_FB_ARMCLCD
611         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
612         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
613                 LPC32XX_CLKPWR_LCDCLK_CTRL);
614 #endif
615 #ifdef CONFIG_SPI_PL022
616         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
617         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
618                 LPC32XX_CLKPWR_SSP_CLK_CTRL);
619 #endif
620
621         platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
622         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
623                 struct amba_device *d = amba_devs[i];
624                 amba_device_register(d, &iomem_resource);
625         }
626
627         /* Test clock needed for UDA1380 initial init */
628         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
629                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
630                 LPC32XX_CLKPWR_TEST_CLK_SEL);
631
632         i2c_register_board_info(0, phy3250_i2c_board_info,
633                 ARRAY_SIZE(phy3250_i2c_board_info));
634 }
635
636 static int __init lpc32xx_display_uid(void)
637 {
638         u32 uid[4];
639
640         lpc32xx_get_uid(uid);
641
642         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
643                 uid[3], uid[2], uid[1], uid[0]);
644
645         return 1;
646 }
647 arch_initcall(lpc32xx_display_uid);
648
649 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
650         /* Maintainer: Kevin Wells, NXP Semiconductors */
651         .phys_io        = LPC32XX_UART5_BASE,
652         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
653         .boot_params    = 0x80000100,
654         .map_io         = lpc32xx_map_io,
655         .init_irq       = lpc32xx_init_irq,
656         .timer          = &lpc32xx_timer,
657         .init_machine   = phy3250_board_init,
658 MACHINE_END
659
660 /* For backwards compatibility with older bootloaders only */
661 MACHINE_START(LPC3XXX, "Phytec 3250 board with the LPC3250 Microcontroller")
662         /* Maintainer: Kevin Wells, NXP Semiconductors */
663         .phys_io        = LPC32XX_UART5_BASE,
664         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
665         .boot_params    = 0x80000100,
666         .map_io         = lpc32xx_map_io,
667         .init_irq       = lpc32xx_init_irq,
668         .timer          = &lpc32xx_timer,
669         .init_machine   = phy3250_board_init,
670 MACHINE_END