mtd: lpc32xx_nand: NAND driver changes
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / phy3250.c
1 /*
2  * arch/arm/mach-lpc32xx/phy3250.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/sysdev.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/device.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/eeprom.h>
28 #include <linux/leds.h>
29 #include <linux/gpio.h>
30 #include <linux/input.h>
31 #include <linux/amba/bus.h>
32 #include <linux/amba/clcd.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/amba/mmci.h>
35 #include <sound/uda1380.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40
41 #include <mach/hardware.h>
42 #include <mach/platform.h>
43 #include <mach/board.h>
44 #include "common.h"
45
46 /*
47  * Mapped GPIOLIB GPIOs
48  */
49 #define SPI0_CS_GPIO            LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
50 #define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
51 #define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
52 #define LED_GPIO                LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
53 #define NAND_WP_GPIO            LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
54 #define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
55 #define MMC_CD_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
56 #define MMC_WP_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
57
58 /*
59  * AMBA LCD controller
60  */
61 static struct clcd_panel conn_lcd_panel = {
62         .mode           = {
63                 .name           = "QVGA portrait",
64                 .refresh        = 60,
65                 .xres           = 240,
66                 .yres           = 320,
67                 .pixclock       = 191828,
68                 .left_margin    = 22,
69                 .right_margin   = 11,
70                 .upper_margin   = 2,
71                 .lower_margin   = 1,
72                 .hsync_len      = 5,
73                 .vsync_len      = 2,
74                 .sync           = 0,
75                 .vmode          = FB_VMODE_NONINTERLACED,
76         },
77         .width          = -1,
78         .height         = -1,
79         .tim2           = (TIM2_IVS | TIM2_IHS),
80         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
81                                 CNTL_LCDBPP16_565),
82         .bpp            = 16,
83 };
84 #define PANEL_SIZE (3 * SZ_64K)
85
86 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
87 {
88         dma_addr_t dma;
89
90         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
91                 PANEL_SIZE, &dma, GFP_KERNEL);
92         if (!fb->fb.screen_base) {
93                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
94                 return -ENOMEM;
95         }
96
97         fb->fb.fix.smem_start = dma;
98         fb->fb.fix.smem_len = PANEL_SIZE;
99         fb->panel = &conn_lcd_panel;
100
101         if (gpio_request(LCD_POWER_GPIO, "LCD power"))
102                 printk(KERN_ERR "Error requesting gpio %u",
103                         LCD_POWER_GPIO);
104         else if (gpio_direction_output(LCD_POWER_GPIO, 1))
105                 printk(KERN_ERR "Error setting gpio %u to output",
106                         LCD_POWER_GPIO);
107
108         if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
109                 printk(KERN_ERR "Error requesting gpio %u",
110                         BKL_POWER_GPIO);
111         else if (gpio_direction_output(BKL_POWER_GPIO, 1))
112                 printk(KERN_ERR "Error setting gpio %u to output",
113                         BKL_POWER_GPIO);
114
115         return 0;
116 }
117
118 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
119 {
120         return dma_mmap_writecombine(&fb->dev->dev, vma,
121                 fb->fb.screen_base, fb->fb.fix.smem_start,
122                 fb->fb.fix.smem_len);
123 }
124
125 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
126 {
127         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
128                 fb->fb.screen_base, fb->fb.fix.smem_start);
129 }
130
131 /*
132  * On some early LCD modules (1307.0), the backlight logic is inverted.
133  * For those board variants, swap the disable and enable states for
134  * BKL_POWER_GPIO.
135 */
136 static void clcd_disable(struct clcd_fb *fb)
137 {
138         gpio_set_value(BKL_POWER_GPIO, 0);
139         gpio_set_value(LCD_POWER_GPIO, 0);
140 }
141
142 static void clcd_enable(struct clcd_fb *fb)
143 {
144         gpio_set_value(BKL_POWER_GPIO, 1);
145         gpio_set_value(LCD_POWER_GPIO, 1);
146 }
147
148 static struct clcd_board lpc32xx_clcd_data = {
149         .name           = "Phytec LCD",
150         .check          = clcdfb_check,
151         .decode         = clcdfb_decode,
152         .disable        = clcd_disable,
153         .enable         = clcd_enable,
154         .setup          = lpc32xx_clcd_setup,
155         .mmap           = lpc32xx_clcd_mmap,
156         .remove         = lpc32xx_clcd_remove,
157 };
158
159 static struct amba_device lpc32xx_clcd_device = {
160         .dev                            = {
161                 .coherent_dma_mask      = ~0,
162                 .init_name              = "dev:clcd",
163                 .platform_data          = &lpc32xx_clcd_data,
164         },
165         .res                            = {
166                 .start                  = LPC32XX_LCD_BASE,
167                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
168                 .flags                  = IORESOURCE_MEM,
169         },
170         .dma_mask                       = ~0,
171         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
172 };
173
174 /*
175  * AMBA SSP (SPI)
176  */
177 static void phy3250_spi_cs_set(u32 control)
178 {
179         gpio_set_value(SPI0_CS_GPIO, (int) control);
180 }
181
182 static struct pl022_config_chip spi0_chip_info = {
183         .lbm                    = LOOPBACK_DISABLED,
184         .com_mode               = INTERRUPT_TRANSFER,
185         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
186         .hierarchy              = SSP_MASTER,
187         .slave_tx_disable       = 0,
188         .endian_tx              = SSP_TX_LSB,
189         .endian_rx              = SSP_RX_LSB,
190         .data_size              = SSP_DATA_BITS_8,
191         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
192         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
193         .clk_phase              = SSP_CLK_FIRST_EDGE,
194         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
195         .ctrl_len               = SSP_BITS_8,
196         .wait_state             = SSP_MWIRE_WAIT_ZERO,
197         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
198         .cs_control             = phy3250_spi_cs_set,
199 };
200
201 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
202         .bus_id                 = 0,
203         .num_chipselect         = 1,
204         .enable_dma             = 0,
205 };
206
207 static struct amba_device lpc32xx_ssp0_device = {
208         .dev                            = {
209                 .coherent_dma_mask      = ~0,
210                 .init_name              = "dev:ssp0",
211                 .platform_data          = &lpc32xx_ssp0_data,
212         },
213         .res                            = {
214                 .start                  = LPC32XX_SSP0_BASE,
215                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
216                 .flags                  = IORESOURCE_MEM,
217         },
218         .dma_mask                       = ~0,
219         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
220 };
221
222 /* AT25 driver registration */
223 static int __init phy3250_spi_board_register(void)
224 {
225 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
226         static struct spi_board_info info[] = {
227                 {
228                         .modalias = "spidev",
229                         .max_speed_hz = 5000000,
230                         .bus_num = 0,
231                         .chip_select = 0,
232                         .controller_data = &spi0_chip_info,
233                 },
234         };
235
236 #else
237         static struct spi_eeprom eeprom = {
238                 .name = "at25256a",
239                 .byte_len = 0x8000,
240                 .page_size = 64,
241                 .flags = EE_ADDR2,
242         };
243
244         static struct spi_board_info info[] = {
245                 {
246                         .modalias = "at25",
247                         .max_speed_hz = 5000000,
248                         .bus_num = 0,
249                         .chip_select = 0,
250                         .platform_data = &eeprom,
251                         .controller_data = &spi0_chip_info,
252                 },
253         };
254 #endif
255         return spi_register_board_info(info, ARRAY_SIZE(info));
256 }
257 arch_initcall(phy3250_spi_board_register);
258
259 /*
260  * Platform Data for UDA1380 Audiocodec.
261  * As there are no GPIOs for codec power & reset pins,
262  * dummy GPIO numbers are used.
263  */
264 static struct uda1380_platform_data uda1380_info = {
265         .gpio_power = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,10),
266         .gpio_reset = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,2),
267         .dac_clk    = UDA1380_DAC_CLK_WSPLL,
268 };
269
270 static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
271         {
272                 I2C_BOARD_INFO("pcf8563", 0x51),
273         },
274         {
275                 I2C_BOARD_INFO("uda1380", 0x18),
276                 .platform_data = &uda1380_info,
277         },
278 };
279
280 static struct gpio_led phy_leds[] = {
281         {
282                 .name                   = "led0",
283                 .gpio                   = LED_GPIO,
284                 .active_low             = 1,
285                 .default_trigger        = "heartbeat",
286         },
287 };
288
289 static struct gpio_led_platform_data led_data = {
290         .leds = phy_leds,
291         .num_leds = ARRAY_SIZE(phy_leds),
292 };
293
294 static struct platform_device lpc32xx_gpio_led_device = {
295         .name                   = "leds-gpio",
296         .id                     = -1,
297         .dev.platform_data      = &led_data,
298 };
299
300 /*
301  * Board specific key scanner driver data
302  */
303 #define PHY3250_KMATRIX_SIZE 1
304 static int lpc32xx_keymaps[] = {
305         KEY_1,  /* 1, 1 */
306 };
307
308 static struct lpc32XX_kscan_cfg lpc32xx_kscancfg = {
309         .matrix_sz      = PHY3250_KMATRIX_SIZE,
310         .keymap         = lpc32xx_keymaps,
311         /* About a 30Hz scan rate based on a 32KHz clock */
312         .deb_clks       = 3,
313         .scan_delay     = 34,
314 };
315
316 static struct resource kscan_resources[] = {
317         [0] = {
318                 .start  = LPC32XX_KSCAN_BASE,
319                 .end    = LPC32XX_KSCAN_BASE + SZ_4K - 1,
320                 .flags  = IORESOURCE_MEM,
321         },
322         [1] = {
323                 .start  = IRQ_LPC32XX_KEY,
324                 .end    = IRQ_LPC32XX_KEY,
325                 .flags  = IORESOURCE_IRQ,
326         },
327
328 };
329
330 static struct platform_device lpc32xx_kscan_device = {
331         .name           = "lpc32xx_keys",
332         .id             = 0,
333         .dev            = {
334                 .platform_data  = &lpc32xx_kscancfg,
335         },
336         .num_resources  = ARRAY_SIZE(kscan_resources),
337         .resource       = kscan_resources,
338 };
339
340 #if defined (CONFIG_MMC_ARMMMCI)
341 static u32 mmc_translate_vdd(struct device *dev, unsigned int vdd)
342 {
343         /* Only on and off are supported */
344         if (vdd != 0)
345                 gpio_set_value(MMC_PWR_ENABLE_GPIO,1);
346         else
347                 gpio_set_value(MMC_PWR_ENABLE_GPIO,0);
348
349         return 0;
350 }
351
352 /*
353  * Board specific MMC driver data
354  */
355 struct mmci_platform_data lpc32xx_plat_data = {
356         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
357         .translate_vdd  = mmc_translate_vdd,
358         .capabilities   = MMC_CAP_4_BIT_DATA,
359         .gpio_wp        = MMC_WP_GPIO,
360         .gpio_cd        = MMC_CD_GPIO,
361 };
362
363 /*
364  * SD card controller resources
365  */
366 struct amba_device lpc32xx_mmc_device = {
367         .dev                            = {
368                 .coherent_dma_mask      = ~0,
369                 .init_name                 = "dev:mmc0",
370                 .platform_data          = &lpc32xx_plat_data,
371         },
372         .res                            = {
373                 .start                  = LPC32XX_SD_BASE,
374                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
375                 .flags                  = IORESOURCE_MEM,
376         },
377         .dma_mask                       = ~0,
378         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
379 };
380 #endif
381
382
383 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
384 /*
385  * Board specific NAND setup data
386  */
387 static int nandwp_enable(int enable)
388 {
389         if (enable != 0)
390                 gpio_set_value(NAND_WP_GPIO,0);
391         else
392                 gpio_set_value(NAND_WP_GPIO,1);
393
394         return 1;
395 }
396 #define BLK_SIZE (512 * 32)
397 static struct mtd_partition phy3250_nand_partition[] = {
398         {
399                 .name   = "phy3250-boot",
400                 .offset = 0,
401                 .size   = (BLK_SIZE * 25)
402         },
403         {
404                 .name   = "phy3250-uboot",
405                 .offset = MTDPART_OFS_APPEND,
406                 .size   = (BLK_SIZE * 100)
407         },
408         {
409                 .name   = "phy3250-ubt-prms",
410                 .offset = MTDPART_OFS_APPEND,
411                 .size   = (BLK_SIZE * 4)
412         },
413         {
414                 .name   = "phy3250-kernel",
415                 .offset = MTDPART_OFS_APPEND,
416                 .size   = (BLK_SIZE * 256)
417         },
418         {
419                 .name   = "phy3250-rootfs",
420                 .offset = MTDPART_OFS_APPEND,
421                 .size   = MTDPART_SIZ_FULL
422         },
423 };
424 static struct mtd_partition * phy3250_nand_partitions(int size, int *num_partitions)
425 {
426         *num_partitions = ARRAY_SIZE(phy3250_nand_partition);
427         return phy3250_nand_partition;
428 }
429 static struct lpc32XX_nand_cfg lpc32xx_nandcfg =
430 {
431         .wdr_clks               = 14,
432         .wwidth                 = 40000000,
433         .whold                  = 100000000,
434         .wsetup                 = 100000000,
435         .rdr_clks               = 14,
436         .rwidth                 = 40000000,
437         .rhold                  = 66666666,
438         .rsetup                 = 100000000,
439         .use_bbt                = true,
440         .polled_completion      = false,
441         .enable_write_prot      = nandwp_enable,
442         .partition_info         = phy3250_nand_partitions,
443 };
444
445 /*
446  * SLC NAND resources
447  */
448 static struct resource slc_nand_resources[] = {
449         [0] = {
450                 .start  = LPC32XX_SLC_BASE,
451                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
452                 .flags  = IORESOURCE_MEM,
453         },
454
455         [1] = {
456                 .start  = IRQ_LPC32XX_FLASH,
457                 .end    = IRQ_LPC32XX_FLASH,
458                 .flags  = IORESOURCE_IRQ,
459         },
460
461 };
462 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
463 static struct platform_device lpc32xx_slc_nand_device = {
464         .name           = "lpc32xx-nand",
465         .id             = 0,
466         .dev            = {
467                                 .platform_data  = &lpc32xx_nandcfg,
468                                 .dma_mask    = &lpc32xx_slc_dma_mask,
469                                 .coherent_dma_mask = ~0UL,
470         },
471         .num_resources  = ARRAY_SIZE(slc_nand_resources),
472         .resource       = slc_nand_resources,
473 };
474 #endif
475
476 /*
477  * Network Support
478  */
479 static struct lpc_net_cfg lpc32xx_netdata =
480 {
481         .phy_irq        = -1,
482         .phy_mask       = 0xFFFFFFF0,
483 };
484
485 static struct resource net_resources[] = {
486         [0] = {
487                 .start  = LPC32XX_ETHERNET_BASE,
488                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
489                 .flags  = IORESOURCE_MEM,
490         },
491
492         [1] = {
493                 .start  = IRQ_LPC32XX_ETHERNET,
494                 .end    = IRQ_LPC32XX_ETHERNET,
495                 .flags  = IORESOURCE_IRQ,
496         },
497
498 };
499
500 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
501 static struct platform_device lpc32xx_net_device = {
502         .name           = "lpc-net",
503         .id             = 0,
504         .dev            = {
505                 .dma_mask = &lpc32xx_mac_dma_mask,
506                 .coherent_dma_mask = 0xffffffffUL,
507                 .platform_data  = &lpc32xx_netdata,
508         },
509         .num_resources  = ARRAY_SIZE(net_resources),
510         .resource       = net_resources,
511 };
512
513 static struct platform_device *phy3250_devs[] __initdata = {
514         &lpc32xx_i2c0_device,
515         &lpc32xx_i2c1_device,
516         &lpc32xx_i2c2_device,
517         &lpc32xx_watchdog_device,
518         &lpc32xx_gpio_led_device,
519         &lpc32xx_rtc_device,
520         &lpc32xx_tsc_device,
521         &lpc32xx_kscan_device,
522         &lpc32xx_net_device,
523 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
524         &lpc32xx_slc_nand_device,
525 #endif
526 #if defined(CONFIG_USB_OHCI_HCD)
527         &lpc32xx_ohci_device,
528 #endif
529 #if defined(CONFIG_USB_GADGET_LPC32XX)
530         &lpc32xx_usbd_device,
531 #endif
532 };
533
534 static struct amba_device *amba_devs[] __initdata = {
535         &lpc32xx_clcd_device,
536         &lpc32xx_ssp0_device,
537 #if defined(CONFIG_MMC_ARMMMCI)
538         &lpc32xx_mmc_device,
539 #endif
540 };
541
542 /*
543  * Board specific functions
544  */
545 static void __init phy3250_board_init(void)
546 {
547         u32 tmp;
548         int i;
549
550         lpc32xx_gpio_init();
551
552         /* Register GPIOs used on this board */
553         if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
554                 printk(KERN_ERR "Error requesting gpio %u",
555                                 SPI0_CS_GPIO);
556         else if (gpio_direction_output(SPI0_CS_GPIO, 1))
557                 printk(KERN_ERR "Error setting gpio %u to output",
558                                 SPI0_CS_GPIO);
559
560         if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
561                 printk(KERN_ERR "Error requesting gpio %u",
562                                 MMC_PWR_ENABLE_GPIO);
563         else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
564                 printk(KERN_ERR "Error setting gpio %u to output",
565                                 MMC_PWR_ENABLE_GPIO);
566
567         /* Setup network interface for RMII mode */
568         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
569         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
570         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
571         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
572
573         /* Setup SLC NAND controller muxing */
574         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
575                 LPC32XX_CLKPWR_NAND_CLK_CTRL);
576
577         /* Setup LCD muxing to RGB565 */
578         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
579                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
580                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
581         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
582         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
583
584         /* Set up I2C pull levels */
585         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
586         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
587                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
588         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
589
590         /* Disable IrDA pulsing support on UART6 */
591         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
592         tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
593         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
594
595         /* Enable DMA for I2S1 channel */
596         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
597         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
598         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
599
600         lpc32xx_serial_init();
601
602         /*
603          * AMBA peripheral clocks need to be enabled prior to AMBA device
604          * detection or a data fault will occur, so enable the clocks
605          * here. However, we don't want to enable them if the peripheral
606          * isn't included in the image
607          */
608 #if defined(CONFIG_MMC_ARMMMCI)
609         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
610         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
611         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
612 #endif
613
614 #ifdef CONFIG_FB_ARMCLCD
615         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
616         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
617                 LPC32XX_CLKPWR_LCDCLK_CTRL);
618 #endif
619 #ifdef CONFIG_SPI_PL022
620         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
621         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
622                 LPC32XX_CLKPWR_SSP_CLK_CTRL);
623 #endif
624
625         platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
626         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
627                 struct amba_device *d = amba_devs[i];
628                 amba_device_register(d, &iomem_resource);
629         }
630
631         /* Test clock needed for UDA1380 initial init */
632         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
633                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
634                 LPC32XX_CLKPWR_TEST_CLK_SEL);
635
636         i2c_register_board_info(0, phy3250_i2c_board_info,
637                 ARRAY_SIZE(phy3250_i2c_board_info));
638 }
639
640 static int __init lpc32xx_display_uid(void)
641 {
642         u32 uid[4];
643
644         lpc32xx_get_uid(uid);
645
646         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
647                 uid[3], uid[2], uid[1], uid[0]);
648
649         return 1;
650 }
651 arch_initcall(lpc32xx_display_uid);
652
653 /*
654  * Example code for setting up the BTN1 button (on GPI3) for system
655  * wakeup and IRQ support. This will allow the GPI3 input to wake
656  * up the system on a low edge. Edge based interrupts won't be
657  * registered in the interrupt controller when the system is asleep,
658  * although they will be registered in the event manager. For this,
659  * reason, a level based interrupt state is recommended for GPIOs when
660  * using IRQ and wakeup from GPI edge state.
661  *
662  */
663 #define BTN1_GPIO               LPC32XX_GPIO(LPC32XX_GPI_P3_GRP, 3)
664 static irqreturn_t phy3250_btn1_irq(int irq, void *dev)
665 {
666         printk(KERN_INFO "GPIO IRQ!\n");
667
668         return IRQ_HANDLED;
669 }
670
671 static int __init phy3250_button_setup(void)
672 {
673         int ret;
674
675         if (gpio_request(BTN1_GPIO, "Button 1")) {
676                 printk(KERN_ERR "Error requesting gpio %u", BTN1_GPIO);
677                 return 0;
678         }
679
680         /*
681          * Wakeup/irq on low edge - the wakeup state will use the same
682          * state as the IRQ edge state.
683          */
684         set_irq_type(IRQ_LPC32XX_GPI_03, IRQ_TYPE_EDGE_FALLING);
685         ret = request_irq(IRQ_LPC32XX_GPI_03, phy3250_btn1_irq,
686                 IRQF_DISABLED, "gpio_btn1_irq", NULL);
687         if (ret < 0) {
688                 printk(KERN_ERR "Can't request interrupt\n");
689                 return 0;
690         }
691
692         enable_irq_wake(IRQ_LPC32XX_GPI_03);
693
694         return 1;
695 }
696 device_initcall(phy3250_button_setup);
697
698 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
699         /* Maintainer: Kevin Wells, NXP Semiconductors */
700         .phys_io        = LPC32XX_UART5_BASE,
701         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
702         .boot_params    = 0x80000100,
703         .map_io         = lpc32xx_map_io,
704         .init_irq       = lpc32xx_init_irq,
705         .timer          = &lpc32xx_timer,
706         .init_machine   = phy3250_board_init,
707 MACHINE_END
708
709 /* For backwards compatibility with older bootloaders only */
710 MACHINE_START(LPC3XXX, "Phytec 3250 board with the LPC3250 Microcontroller")
711         /* Maintainer: Kevin Wells, NXP Semiconductors */
712         .phys_io        = LPC32XX_UART5_BASE,
713         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
714         .boot_params    = 0x80000100,
715         .map_io         = lpc32xx_map_io,
716         .init_irq       = lpc32xx_init_irq,
717         .timer          = &lpc32xx_timer,
718         .init_machine   = phy3250_board_init,
719 MACHINE_END