arm:lpc32xx:spi/pl022 Add spi->mode support AMBA SPI driver
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / phy3250.c
1 /*
2  * arch/arm/mach-lpc32xx/phy3250.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/sysdev.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/device.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/eeprom.h>
28 #include <linux/leds.h>
29 #include <linux/gpio.h>
30 #include <linux/input.h>
31 #include <linux/amba/bus.h>
32 #include <linux/amba/clcd.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/amba/mmci.h>
35 #include <sound/uda1380.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40
41 #include <mach/hardware.h>
42 #include <mach/platform.h>
43 #include <mach/board.h>
44 #include "common.h"
45
46 /*
47  * Mapped GPIOLIB GPIOs
48  */
49 #define SPI0_CS_GPIO            LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
50 #define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
51 #define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
52 #define LED_GPIO                LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
53 #define NAND_WP_GPIO            LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
54 #define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
55 #define MMC_CD_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
56 #define MMC_WP_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
57
58 /*
59  * AMBA LCD controller
60  */
61 static struct clcd_panel conn_lcd_panel = {
62         .mode           = {
63                 .name           = "QVGA portrait",
64                 .refresh        = 60,
65                 .xres           = 240,
66                 .yres           = 320,
67                 .pixclock       = 191828,
68                 .left_margin    = 22,
69                 .right_margin   = 11,
70                 .upper_margin   = 2,
71                 .lower_margin   = 1,
72                 .hsync_len      = 5,
73                 .vsync_len      = 2,
74                 .sync           = 0,
75                 .vmode          = FB_VMODE_NONINTERLACED,
76         },
77         .width          = -1,
78         .height         = -1,
79         .tim2           = (TIM2_IVS | TIM2_IHS),
80         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
81                                 CNTL_LCDBPP16_565),
82         .bpp            = 16,
83 };
84 #define PANEL_SIZE (3 * SZ_64K)
85
86 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
87 {
88         dma_addr_t dma;
89
90         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
91                 PANEL_SIZE, &dma, GFP_KERNEL);
92         if (!fb->fb.screen_base) {
93                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
94                 return -ENOMEM;
95         }
96
97         fb->fb.fix.smem_start = dma;
98         fb->fb.fix.smem_len = PANEL_SIZE;
99         fb->panel = &conn_lcd_panel;
100
101         if (gpio_request(LCD_POWER_GPIO, "LCD power"))
102                 printk(KERN_ERR "Error requesting gpio %u",
103                         LCD_POWER_GPIO);
104         else if (gpio_direction_output(LCD_POWER_GPIO, 1))
105                 printk(KERN_ERR "Error setting gpio %u to output",
106                         LCD_POWER_GPIO);
107
108         if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
109                 printk(KERN_ERR "Error requesting gpio %u",
110                         BKL_POWER_GPIO);
111         else if (gpio_direction_output(BKL_POWER_GPIO, 1))
112                 printk(KERN_ERR "Error setting gpio %u to output",
113                         BKL_POWER_GPIO);
114
115         return 0;
116 }
117
118 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
119 {
120         return dma_mmap_writecombine(&fb->dev->dev, vma,
121                 fb->fb.screen_base, fb->fb.fix.smem_start,
122                 fb->fb.fix.smem_len);
123 }
124
125 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
126 {
127         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
128                 fb->fb.screen_base, fb->fb.fix.smem_start);
129 }
130
131 /*
132  * On some early LCD modules (1307.0), the backlight logic is inverted.
133  * For those board variants, swap the disable and enable states for
134  * BKL_POWER_GPIO.
135 */
136 static void clcd_disable(struct clcd_fb *fb)
137 {
138         gpio_set_value(BKL_POWER_GPIO, 0);
139         gpio_set_value(LCD_POWER_GPIO, 0);
140 }
141
142 static void clcd_enable(struct clcd_fb *fb)
143 {
144         gpio_set_value(BKL_POWER_GPIO, 1);
145         gpio_set_value(LCD_POWER_GPIO, 1);
146 }
147
148 static struct clcd_board lpc32xx_clcd_data = {
149         .name           = "Phytec LCD",
150         .check          = clcdfb_check,
151         .decode         = clcdfb_decode,
152         .disable        = clcd_disable,
153         .enable         = clcd_enable,
154         .setup          = lpc32xx_clcd_setup,
155         .mmap           = lpc32xx_clcd_mmap,
156         .remove         = lpc32xx_clcd_remove,
157 };
158
159 static struct amba_device lpc32xx_clcd_device = {
160         .dev                            = {
161                 .coherent_dma_mask      = ~0,
162                 .init_name              = "dev:clcd",
163                 .platform_data          = &lpc32xx_clcd_data,
164         },
165         .res                            = {
166                 .start                  = LPC32XX_LCD_BASE,
167                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
168                 .flags                  = IORESOURCE_MEM,
169         },
170         .dma_mask                       = ~0,
171         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
172 };
173
174 /*
175  * AMBA SSP (SPI)
176  */
177 static void phy3250_spi_cs_set(u32 control)
178 {
179         gpio_set_value(SPI0_CS_GPIO, (int) control);
180 }
181
182 static struct pl022_config_chip spi0_chip_info = {
183         .com_mode               = INTERRUPT_TRANSFER,
184         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
185         .hierarchy              = SSP_MASTER,
186         .slave_tx_disable       = 0,
187         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
188         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
189         .ctrl_len               = SSP_BITS_8,
190         .wait_state             = SSP_MWIRE_WAIT_ZERO,
191         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
192         .cs_control             = phy3250_spi_cs_set,
193 };
194
195 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
196         .bus_id                 = 0,
197         .num_chipselect         = 1,
198         .enable_dma             = 0,
199 };
200
201 static struct amba_device lpc32xx_ssp0_device = {
202         .dev                            = {
203                 .coherent_dma_mask      = ~0,
204                 .init_name              = "dev:ssp0",
205                 .platform_data          = &lpc32xx_ssp0_data,
206         },
207         .res                            = {
208                 .start                  = LPC32XX_SSP0_BASE,
209                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
210                 .flags                  = IORESOURCE_MEM,
211         },
212         .dma_mask                       = ~0,
213         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
214 };
215
216 /* AT25 driver registration */
217 static int __init phy3250_spi_board_register(void)
218 {
219 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
220         static struct spi_board_info info[] = {
221                 {
222                         .modalias = "spidev",
223                         .max_speed_hz = 5000000,
224                         .bus_num = 0,
225                         .chip_select = 0,
226                         .controller_data = &spi0_chip_info,
227                 },
228         };
229
230 #else
231         static struct spi_eeprom eeprom = {
232                 .name = "at25256a",
233                 .byte_len = 0x8000,
234                 .page_size = 64,
235                 .flags = EE_ADDR2,
236         };
237
238         static struct spi_board_info info[] = {
239                 {
240                         .modalias = "at25",
241                         .max_speed_hz = 5000000,
242                         .bus_num = 0,
243                         .chip_select = 0,
244                         .mode = SPI_MODE_0,
245                         .platform_data = &eeprom,
246                         .controller_data = &spi0_chip_info,
247                 },
248         };
249 #endif
250         return spi_register_board_info(info, ARRAY_SIZE(info));
251 }
252 arch_initcall(phy3250_spi_board_register);
253
254 /*
255  * Platform Data for UDA1380 Audiocodec.
256  * As there are no GPIOs for codec power & reset pins,
257  * dummy GPIO numbers are used.
258  */
259 static struct uda1380_platform_data uda1380_info = {
260         .gpio_power = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,10),
261         .gpio_reset = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,2),
262         .dac_clk    = UDA1380_DAC_CLK_WSPLL,
263 };
264
265 static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
266         {
267                 I2C_BOARD_INFO("pcf8563", 0x51),
268         },
269         {
270                 I2C_BOARD_INFO("uda1380", 0x18),
271                 .platform_data = &uda1380_info,
272         },
273 };
274
275 static struct gpio_led phy_leds[] = {
276         {
277                 .name                   = "led0",
278                 .gpio                   = LED_GPIO,
279                 .active_low             = 1,
280                 .default_trigger        = "heartbeat",
281         },
282 };
283
284 static struct gpio_led_platform_data led_data = {
285         .leds = phy_leds,
286         .num_leds = ARRAY_SIZE(phy_leds),
287 };
288
289 static struct platform_device lpc32xx_gpio_led_device = {
290         .name                   = "leds-gpio",
291         .id                     = -1,
292         .dev.platform_data      = &led_data,
293 };
294
295 /*
296  * Board specific key scanner driver data
297  */
298 #define PHY3250_KMATRIX_SIZE 1
299 static int lpc32xx_keymaps[] = {
300         KEY_1,  /* 1, 1 */
301 };
302
303 static struct lpc32XX_kscan_cfg lpc32xx_kscancfg = {
304         .matrix_sz      = PHY3250_KMATRIX_SIZE,
305         .keymap         = lpc32xx_keymaps,
306         /* About a 30Hz scan rate based on a 32KHz clock */
307         .deb_clks       = 3,
308         .scan_delay     = 34,
309 };
310
311 static struct resource kscan_resources[] = {
312         [0] = {
313                 .start  = LPC32XX_KSCAN_BASE,
314                 .end    = LPC32XX_KSCAN_BASE + SZ_4K - 1,
315                 .flags  = IORESOURCE_MEM,
316         },
317         [1] = {
318                 .start  = IRQ_LPC32XX_KEY,
319                 .end    = IRQ_LPC32XX_KEY,
320                 .flags  = IORESOURCE_IRQ,
321         },
322
323 };
324
325 static struct platform_device lpc32xx_kscan_device = {
326         .name           = "lpc32xx_keys",
327         .id             = 0,
328         .dev            = {
329                 .platform_data  = &lpc32xx_kscancfg,
330         },
331         .num_resources  = ARRAY_SIZE(kscan_resources),
332         .resource       = kscan_resources,
333 };
334
335 #if defined (CONFIG_MMC_ARMMMCI)
336 static u32 mmc_translate_vdd(struct device *dev, unsigned int vdd)
337 {
338         /* Only on and off are supported */
339         if (vdd != 0)
340                 gpio_set_value(MMC_PWR_ENABLE_GPIO,1);
341         else
342                 gpio_set_value(MMC_PWR_ENABLE_GPIO,0);
343
344         return 0;
345 }
346
347 /*
348  * Board specific MMC driver data
349  */
350 struct mmci_platform_data lpc32xx_plat_data = {
351         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
352         .translate_vdd  = mmc_translate_vdd,
353         .capabilities   = MMC_CAP_4_BIT_DATA,
354         .gpio_wp        = MMC_WP_GPIO,
355         .gpio_cd        = MMC_CD_GPIO,
356 };
357
358 /*
359  * SD card controller resources
360  */
361 struct amba_device lpc32xx_mmc_device = {
362         .dev                            = {
363                 .coherent_dma_mask      = ~0,
364                 .init_name                 = "dev:mmc0",
365                 .platform_data          = &lpc32xx_plat_data,
366         },
367         .res                            = {
368                 .start                  = LPC32XX_SD_BASE,
369                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
370                 .flags                  = IORESOURCE_MEM,
371         },
372         .dma_mask                       = ~0,
373         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
374 };
375 #endif
376
377
378 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
379 /*
380  * Board specific NAND setup data
381  */
382 static int nandwp_enable(int enable)
383 {
384         if (enable != 0)
385                 gpio_set_value(NAND_WP_GPIO,0);
386         else
387                 gpio_set_value(NAND_WP_GPIO,1);
388
389         return 1;
390 }
391 #define BLK_SIZE (512 * 32)
392 static struct mtd_partition phy3250_nand_partition[] = {
393         {
394                 .name   = "phy3250-boot",
395                 .offset = 0,
396                 .size   = (BLK_SIZE * 25)
397         },
398         {
399                 .name   = "phy3250-uboot",
400                 .offset = MTDPART_OFS_APPEND,
401                 .size   = (BLK_SIZE * 100)
402         },
403         {
404                 .name   = "phy3250-ubt-prms",
405                 .offset = MTDPART_OFS_APPEND,
406                 .size   = (BLK_SIZE * 4)
407         },
408         {
409                 .name   = "phy3250-kernel",
410                 .offset = MTDPART_OFS_APPEND,
411                 .size   = (BLK_SIZE * 256)
412         },
413         {
414                 .name   = "phy3250-rootfs",
415                 .offset = MTDPART_OFS_APPEND,
416                 .size   = MTDPART_SIZ_FULL
417         },
418 };
419 static struct mtd_partition * phy3250_nand_partitions(int size, int *num_partitions)
420 {
421         *num_partitions = ARRAY_SIZE(phy3250_nand_partition);
422         return phy3250_nand_partition;
423 }
424 static struct lpc32XX_nand_cfg lpc32xx_nandcfg =
425 {
426         .wdr_clks               = 14,
427         .wwidth                 = 40000000,
428         .whold                  = 100000000,
429         .wsetup                 = 100000000,
430         .rdr_clks               = 14,
431         .rwidth                 = 40000000,
432         .rhold                  = 66666666,
433         .rsetup                 = 100000000,
434         .use_bbt                = true,
435         .polled_completion      = false,
436         .enable_write_prot      = nandwp_enable,
437         .partition_info         = phy3250_nand_partitions,
438 };
439
440 /*
441  * SLC NAND resources
442  */
443 static struct resource slc_nand_resources[] = {
444         [0] = {
445                 .start  = LPC32XX_SLC_BASE,
446                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
447                 .flags  = IORESOURCE_MEM,
448         },
449
450         [1] = {
451                 .start  = IRQ_LPC32XX_FLASH,
452                 .end    = IRQ_LPC32XX_FLASH,
453                 .flags  = IORESOURCE_IRQ,
454         },
455
456 };
457 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
458 static struct platform_device lpc32xx_slc_nand_device = {
459         .name           = "lpc32xx-nand",
460         .id             = 0,
461         .dev            = {
462                                 .platform_data  = &lpc32xx_nandcfg,
463                                 .dma_mask    = &lpc32xx_slc_dma_mask,
464                                 .coherent_dma_mask = ~0UL,
465         },
466         .num_resources  = ARRAY_SIZE(slc_nand_resources),
467         .resource       = slc_nand_resources,
468 };
469 #endif
470
471 /*
472  * Network Support
473  */
474 static struct lpc_net_cfg lpc32xx_netdata =
475 {
476         .phy_irq        = -1,
477         .phy_mask       = 0xFFFFFFF0,
478 };
479
480 static struct resource net_resources[] = {
481         [0] = {
482                 .start  = LPC32XX_ETHERNET_BASE,
483                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
484                 .flags  = IORESOURCE_MEM,
485         },
486
487         [1] = {
488                 .start  = IRQ_LPC32XX_ETHERNET,
489                 .end    = IRQ_LPC32XX_ETHERNET,
490                 .flags  = IORESOURCE_IRQ,
491         },
492
493 };
494
495 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
496 static struct platform_device lpc32xx_net_device = {
497         .name           = "lpc-net",
498         .id             = 0,
499         .dev            = {
500                 .dma_mask = &lpc32xx_mac_dma_mask,
501                 .coherent_dma_mask = 0xffffffffUL,
502                 .platform_data  = &lpc32xx_netdata,
503         },
504         .num_resources  = ARRAY_SIZE(net_resources),
505         .resource       = net_resources,
506 };
507
508 static struct platform_device *phy3250_devs[] __initdata = {
509         &lpc32xx_i2c0_device,
510         &lpc32xx_i2c1_device,
511         &lpc32xx_i2c2_device,
512         &lpc32xx_watchdog_device,
513         &lpc32xx_gpio_led_device,
514         &lpc32xx_rtc_device,
515         &lpc32xx_tsc_device,
516         &lpc32xx_kscan_device,
517         &lpc32xx_net_device,
518 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
519         &lpc32xx_slc_nand_device,
520 #endif
521 #if defined(CONFIG_USB_OHCI_HCD)
522         &lpc32xx_ohci_device,
523 #endif
524 #if defined(CONFIG_USB_GADGET_LPC32XX)
525         &lpc32xx_usbd_device,
526 #endif
527 };
528
529 static struct amba_device *amba_devs[] __initdata = {
530         &lpc32xx_clcd_device,
531         &lpc32xx_ssp0_device,
532 #if defined(CONFIG_MMC_ARMMMCI)
533         &lpc32xx_mmc_device,
534 #endif
535 };
536
537 /*
538  * Board specific functions
539  */
540 static void __init phy3250_board_init(void)
541 {
542         u32 tmp;
543         int i;
544
545         lpc32xx_gpio_init();
546
547         /* Register GPIOs used on this board */
548         if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
549                 printk(KERN_ERR "Error requesting gpio %u",
550                                 SPI0_CS_GPIO);
551         else if (gpio_direction_output(SPI0_CS_GPIO, 1))
552                 printk(KERN_ERR "Error setting gpio %u to output",
553                                 SPI0_CS_GPIO);
554
555         if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
556                 printk(KERN_ERR "Error requesting gpio %u",
557                                 MMC_PWR_ENABLE_GPIO);
558         else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
559                 printk(KERN_ERR "Error setting gpio %u to output",
560                                 MMC_PWR_ENABLE_GPIO);
561
562         /* Setup network interface for RMII mode */
563         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
564         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
565         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
566         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
567
568         /* Setup SLC NAND controller muxing */
569         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
570                 LPC32XX_CLKPWR_NAND_CLK_CTRL);
571
572         /* Setup LCD muxing to RGB565 */
573         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
574                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
575                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
576         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
577         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
578
579         /* Set up I2C pull levels */
580         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
581         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
582                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
583         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
584
585         /* Disable IrDA pulsing support on UART6 */
586         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
587         tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
588         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
589
590         /* Enable DMA for I2S1 channel */
591         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
592         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
593         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
594
595         lpc32xx_serial_init();
596
597         /*
598          * AMBA peripheral clocks need to be enabled prior to AMBA device
599          * detection or a data fault will occur, so enable the clocks
600          * here. However, we don't want to enable them if the peripheral
601          * isn't included in the image
602          */
603 #if defined(CONFIG_MMC_ARMMMCI)
604         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
605         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
606         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
607 #endif
608
609 #ifdef CONFIG_FB_ARMCLCD
610         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
611         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
612                 LPC32XX_CLKPWR_LCDCLK_CTRL);
613 #endif
614 #ifdef CONFIG_SPI_PL022
615         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
616         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
617                 LPC32XX_CLKPWR_SSP_CLK_CTRL);
618 #endif
619
620         platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
621         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
622                 struct amba_device *d = amba_devs[i];
623                 amba_device_register(d, &iomem_resource);
624         }
625
626         /* Test clock needed for UDA1380 initial init */
627         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
628                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
629                 LPC32XX_CLKPWR_TEST_CLK_SEL);
630
631         i2c_register_board_info(0, phy3250_i2c_board_info,
632                 ARRAY_SIZE(phy3250_i2c_board_info));
633 }
634
635 static int __init lpc32xx_display_uid(void)
636 {
637         u32 uid[4];
638
639         lpc32xx_get_uid(uid);
640
641         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
642                 uid[3], uid[2], uid[1], uid[0]);
643
644         return 1;
645 }
646 arch_initcall(lpc32xx_display_uid);
647
648 /*
649  * Example code for setting up the BTN1 button (on GPI3) for system
650  * wakeup and IRQ support. This will allow the GPI3 input to wake
651  * up the system on a low edge. Edge based interrupts won't be
652  * registered in the interrupt controller when the system is asleep,
653  * although they will be registered in the event manager. For this,
654  * reason, a level based interrupt state is recommended for GPIOs when
655  * using IRQ and wakeup from GPI edge state.
656  *
657  */
658 #define BTN1_GPIO               LPC32XX_GPIO(LPC32XX_GPI_P3_GRP, 3)
659 static irqreturn_t phy3250_btn1_irq(int irq, void *dev)
660 {
661         printk(KERN_INFO "GPIO IRQ!\n");
662
663         return IRQ_HANDLED;
664 }
665
666 static int __init phy3250_button_setup(void)
667 {
668         int ret;
669
670         if (gpio_request(BTN1_GPIO, "Button 1")) {
671                 printk(KERN_ERR "Error requesting gpio %u", BTN1_GPIO);
672                 return 0;
673         }
674
675         /*
676          * Wakeup/irq on low edge - the wakeup state will use the same
677          * state as the IRQ edge state.
678          */
679         set_irq_type(IRQ_LPC32XX_GPI_03, IRQ_TYPE_EDGE_FALLING);
680         ret = request_irq(IRQ_LPC32XX_GPI_03, phy3250_btn1_irq,
681                 IRQF_DISABLED, "gpio_btn1_irq", NULL);
682         if (ret < 0) {
683                 printk(KERN_ERR "Can't request interrupt\n");
684                 return 0;
685         }
686
687         enable_irq_wake(IRQ_LPC32XX_GPI_03);
688
689         return 1;
690 }
691 device_initcall(phy3250_button_setup);
692
693 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
694         /* Maintainer: Kevin Wells, NXP Semiconductors */
695         .phys_io        = LPC32XX_UART5_BASE,
696         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
697         .boot_params    = 0x80000100,
698         .map_io         = lpc32xx_map_io,
699         .init_irq       = lpc32xx_init_irq,
700         .timer          = &lpc32xx_timer,
701         .init_machine   = phy3250_board_init,
702 MACHINE_END
703
704 /* For backwards compatibility with older bootloaders only */
705 MACHINE_START(LPC3XXX, "Phytec 3250 board with the LPC3250 Microcontroller")
706         /* Maintainer: Kevin Wells, NXP Semiconductors */
707         .phys_io        = LPC32XX_UART5_BASE,
708         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
709         .boot_params    = 0x80000100,
710         .map_io         = lpc32xx_map_io,
711         .init_irq       = lpc32xx_init_irq,
712         .timer          = &lpc32xx_timer,
713         .init_machine   = phy3250_board_init,
714 MACHINE_END