arch/arm/mach-lpc32xx/phy3250.c

   1 /*
   2  * arch/arm/mach-lpc32xx/phy3250.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/device.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/eeprom.h>
  28 #include <linux/leds.h>
  29 #include <linux/gpio.h>
  30 #include <linux/input.h>
  31 #include <linux/amba/bus.h>
  32 #include <linux/amba/clcd.h>
  33 #include <linux/amba/pl022.h>
  34 #include <linux/amba/mmci.h>
  35 #include <sound/uda1380.h>
  36
  37 #include <asm/setup.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/mach/arch.h>
  40
  41 #include <mach/hardware.h>
  42 #include <mach/platform.h>
  43 #include <mach/board.h>
  44 #include "common.h"
  45
  46 /*
  47  * Mapped GPIOLIB GPIOs
  48  */
  49 #define SPI0_CS_GPIO            LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
  50 #define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
  51 #define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
  52 #define LED_GPIO                LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
  53 #define NAND_WP_GPIO            LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
  54 #define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
  55 #define MMC_CD_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
  56 #define MMC_WP_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
  57
  58 /*
  59  * AMBA LCD controller
  60  */
  61 static struct clcd_panel conn_lcd_panel = {
  62         .mode           = {
  63                 .name           = "QVGA portrait",
  64                 .refresh        = 60,
  65                 .xres           = 240,
  66                 .yres           = 320,
  67                 .pixclock       = 191828,
  68                 .left_margin    = 22,
  69                 .right_margin   = 11,
  70                 .upper_margin   = 2,
  71                 .lower_margin   = 1,
  72                 .hsync_len      = 5,
  73                 .vsync_len      = 2,
  74                 .sync           = 0,
  75                 .vmode          = FB_VMODE_NONINTERLACED,
  76         },
  77         .width          = -1,
  78         .height         = -1,
  79         .tim2           = (TIM2_IVS | TIM2_IHS),
  80         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
  81                                 CNTL_LCDBPP16_565),
  82         .bpp            = 16,
  83 };
  84 #define PANEL_SIZE (3 * SZ_64K)
  85
  86 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
  87 {
  88         dma_addr_t dma;
  89
  90         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
  91                 PANEL_SIZE, &dma, GFP_KERNEL);
  92         if (!fb->fb.screen_base) {
  93                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
  94                 return -ENOMEM;
  95         }
  96
  97         fb->fb.fix.smem_start = dma;
  98         fb->fb.fix.smem_len = PANEL_SIZE;
  99         fb->panel = &conn_lcd_panel;
 100
 101         if (gpio_request(LCD_POWER_GPIO, "LCD power"))
 102                 printk(KERN_ERR "Error requesting gpio %u",
 103                         LCD_POWER_GPIO);
 104         else if (gpio_direction_output(LCD_POWER_GPIO, 1))
 105                 printk(KERN_ERR "Error setting gpio %u to output",
 106                         LCD_POWER_GPIO);
 107
 108         if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
 109                 printk(KERN_ERR "Error requesting gpio %u",
 110                         BKL_POWER_GPIO);
 111         else if (gpio_direction_output(BKL_POWER_GPIO, 1))
 112                 printk(KERN_ERR "Error setting gpio %u to output",
 113                         BKL_POWER_GPIO);
 114
 115         return 0;
 116 }
 117
 118 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 119 {
 120         return dma_mmap_writecombine(&fb->dev->dev, vma,
 121                 fb->fb.screen_base, fb->fb.fix.smem_start,
 122                 fb->fb.fix.smem_len);
 123 }
 124
 125 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
 126 {
 127         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 128                 fb->fb.screen_base, fb->fb.fix.smem_start);
 129 }
 130
 131 /*
 132  * On some early LCD modules (1307.0), the backlight logic is inverted.
 133  * For those board variants, swap the disable and enable states for
 134  * BKL_POWER_GPIO.
 135 */
 136 static void clcd_disable(struct clcd_fb *fb)
 137 {
 138         gpio_set_value(BKL_POWER_GPIO, 0);
 139         gpio_set_value(LCD_POWER_GPIO, 0);
 140 }
 141
 142 static void clcd_enable(struct clcd_fb *fb)
 143 {
 144         gpio_set_value(BKL_POWER_GPIO, 1);
 145         gpio_set_value(LCD_POWER_GPIO, 1);
 146 }
 147
 148 static struct clcd_board lpc32xx_clcd_data = {
 149         .name           = "Phytec LCD",
 150         .check          = clcdfb_check,
 151         .decode         = clcdfb_decode,
 152         .disable        = clcd_disable,
 153         .enable         = clcd_enable,
 154         .setup          = lpc32xx_clcd_setup,
 155         .mmap           = lpc32xx_clcd_mmap,
 156         .remove         = lpc32xx_clcd_remove,
 157 };
 158
 159 static struct amba_device lpc32xx_clcd_device = {
 160         .dev                            = {
 161                 .coherent_dma_mask      = ~0,
 162                 .init_name              = "dev:clcd",
 163                 .platform_data          = &lpc32xx_clcd_data,
 164         },
 165         .res                            = {
 166                 .start                  = LPC32XX_LCD_BASE,
 167                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
 168                 .flags                  = IORESOURCE_MEM,
 169         },
 170         .dma_mask                       = ~0,
 171         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
 172 };
 173
 174 /*
 175  * AMBA SSP (SPI)
 176  */
 177 static void phy3250_spi_cs_set(u32 control)
 178 {
 179         gpio_set_value(SPI0_CS_GPIO, (int) control);
 180 }
 181
 182 static struct pl022_config_chip spi0_chip_info = {
 183         .lbm                    = LOOPBACK_DISABLED,
 184         .com_mode               = INTERRUPT_TRANSFER,
 185         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
 186         .hierarchy              = SSP_MASTER,
 187         .slave_tx_disable       = 0,
 188         .endian_tx              = SSP_TX_LSB,
 189         .endian_rx              = SSP_RX_LSB,
 190         .data_size              = SSP_DATA_BITS_8,
 191         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
 192         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
 193         .clk_phase              = SSP_CLK_FIRST_EDGE,
 194         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
 195         .ctrl_len               = SSP_BITS_8,
 196         .wait_state             = SSP_MWIRE_WAIT_ZERO,
 197         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
 198         .cs_control             = phy3250_spi_cs_set,
 199 };
 200
 201 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
 202         .bus_id                 = 0,
 203         .num_chipselect         = 1,
 204         .enable_dma             = 0,
 205 };
 206
 207 static struct amba_device lpc32xx_ssp0_device = {
 208         .dev                            = {
 209                 .coherent_dma_mask      = ~0,
 210                 .init_name              = "dev:ssp0",
 211                 .platform_data          = &lpc32xx_ssp0_data,
 212         },
 213         .res                            = {
 214                 .start                  = LPC32XX_SSP0_BASE,
 215                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
 216                 .flags                  = IORESOURCE_MEM,
 217         },
 218         .dma_mask                       = ~0,
 219         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
 220 };
 221
 222 /* AT25 driver registration */
 223 static int __init phy3250_spi_board_register(void)
 224 {
 225 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 226         static struct spi_board_info info[] = {
 227                 {
 228                         .modalias = "spidev",
 229                         .max_speed_hz = 5000000,
 230                         .bus_num = 0,
 231                         .chip_select = 0,
 232                         .controller_data = &spi0_chip_info,
 233                 },
 234         };
 235
 236 #else
 237         static struct spi_eeprom eeprom = {
 238                 .name = "at25256a",
 239                 .byte_len = 0x8000,
 240                 .page_size = 64,
 241                 .flags = EE_ADDR2,
 242         };
 243
 244         static struct spi_board_info info[] = {
 245                 {
 246                         .modalias = "at25",
 247                         .max_speed_hz = 5000000,
 248                         .bus_num = 0,
 249                         .chip_select = 0,
 250                         .platform_data = &eeprom,
 251                         .controller_data = &spi0_chip_info,
 252                 },
 253         };
 254 #endif
 255         return spi_register_board_info(info, ARRAY_SIZE(info));
 256 }
 257 arch_initcall(phy3250_spi_board_register);
 258
 259 /*
 260  * Platform Data for UDA1380 Audiocodec.
 261  * As there are no GPIOs for codec power & reset pins,
 262  * dummy GPIO numbers are used.
 263  */
 264 static struct uda1380_platform_data uda1380_info = {
 265         .gpio_power = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,10),
 266         .gpio_reset = LPC32XX_GPIO(LPC32XX_GPO_P3_GRP,2),
 267         .dac_clk    = UDA1380_DAC_CLK_WSPLL,
 268 };
 269
 270 static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
 271         {
 272                 I2C_BOARD_INFO("pcf8563", 0x51),
 273         },
 274         {
 275                 I2C_BOARD_INFO("uda1380", 0x18),
 276                 .platform_data = &uda1380_info,
 277         },
 278 };
 279
 280 static struct gpio_led phy_leds[] = {
 281         {
 282                 .name                   = "led0",
 283                 .gpio                   = LED_GPIO,
 284                 .active_low             = 1,
 285                 .default_trigger        = "heartbeat",
 286         },
 287 };
 288
 289 static struct gpio_led_platform_data led_data = {
 290         .leds = phy_leds,
 291         .num_leds = ARRAY_SIZE(phy_leds),
 292 };
 293
 294 static struct platform_device lpc32xx_gpio_led_device = {
 295         .name                   = "leds-gpio",
 296         .id                     = -1,
 297         .dev.platform_data      = &led_data,
 298 };
 299
 300 /*
 301  * Board specific key scanner driver data
 302  */
 303 #define PHY3250_KMATRIX_SIZE 1
 304 static int lpc32xx_keymaps[] = {
 305         KEY_1,  /* 1, 1 */
 306 };
 307
 308 static struct lpc32XX_kscan_cfg lpc32xx_kscancfg = {
 309         .matrix_sz      = PHY3250_KMATRIX_SIZE,
 310         .keymap         = lpc32xx_keymaps,
 311         /* About a 30Hz scan rate based on a 32KHz clock */
 312         .deb_clks       = 3,
 313         .scan_delay     = 34,
 314 };
 315
 316 static struct resource kscan_resources[] = {
 317         [0] = {
 318                 .start  = LPC32XX_KSCAN_BASE,
 319                 .end    = LPC32XX_KSCAN_BASE + SZ_4K - 1,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = IRQ_LPC32XX_KEY,
 324                 .end    = IRQ_LPC32XX_KEY,
 325                 .flags  = IORESOURCE_IRQ,
 326         },
 327
 328 };
 329
 330 static struct platform_device lpc32xx_kscan_device = {
 331         .name           = "lpc32xx_keys",
 332         .id             = 0,
 333         .dev            = {
 334                 .platform_data  = &lpc32xx_kscancfg,
 335         },
 336         .num_resources  = ARRAY_SIZE(kscan_resources),
 337         .resource       = kscan_resources,
 338 };
 339
 340 #if defined (CONFIG_MMC_ARMMMCI)
 341 static u32 mmc_translate_vdd(struct device *dev, unsigned int vdd)
 342 {
 343         /* Only on and off are supported */
 344         if (vdd != 0)
 345                 gpio_set_value(MMC_PWR_ENABLE_GPIO,1);
 346         else
 347                 gpio_set_value(MMC_PWR_ENABLE_GPIO,0);
 348
 349         return 0;
 350 }
 351
 352 /*
 353  * Board specific MMC driver data
 354  */
 355 struct mmci_platform_data lpc32xx_plat_data = {
 356         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
 357         .translate_vdd  = mmc_translate_vdd,
 358         .capabilities   = MMC_CAP_4_BIT_DATA,
 359         .gpio_wp        = MMC_WP_GPIO,
 360         .gpio_cd        = MMC_CD_GPIO,
 361 };
 362
 363 /*
 364  * SD card controller resources
 365  */
 366 struct amba_device lpc32xx_mmc_device = {
 367         .dev                            = {
 368                 .coherent_dma_mask      = ~0,
 369                 .init_name                 = "dev:mmc0",
 370                 .platform_data          = &lpc32xx_plat_data,
 371         },
 372         .res                            = {
 373                 .start                  = LPC32XX_SD_BASE,
 374                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
 375                 .flags                  = IORESOURCE_MEM,
 376         },
 377         .dma_mask                       = ~0,
 378         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
 379 };
 380 #endif
 381
 382
 383 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
 384 /*
 385  * Board specific NAND setup data
 386  */
 387 static int nandwp_enable(int enable)
 388 {
 389         if (enable != 0)
 390                 gpio_set_value(NAND_WP_GPIO,0);
 391         else
 392                 gpio_set_value(NAND_WP_GPIO,1);
 393
 394         return 1;
 395 }
 396 #define BLK_SIZE (512 * 32)
 397 static struct mtd_partition __initdata phy3250_nand_partition[] = {
 398         {
 399                 .name   = "phy3250-boot",
 400                 .offset = 0,
 401                 .size   = (BLK_SIZE * 25)
 402         },
 403         {
 404                 .name   = "phy3250-uboot",
 405                 .offset = MTDPART_OFS_APPEND,
 406                 .size   = (BLK_SIZE * 100)
 407         },
 408         {
 409                 .name   = "phy3250-ubt-prms",
 410                 .offset = MTDPART_OFS_APPEND,
 411                 .size   = (BLK_SIZE * 4)
 412         },
 413         {
 414                 .name   = "phy3250-kernel",
 415                 .offset = MTDPART_OFS_APPEND,
 416                 .size   = (BLK_SIZE * 256)
 417         },
 418         {
 419                 .name   = "phy3250-rootfs",
 420                 .offset = MTDPART_OFS_APPEND,
 421                 .size   = MTDPART_SIZ_FULL
 422         },
 423 };
 424 static struct mtd_partition * __init phy3250_nand_partitions(int size, int *num_partitions)
 425 {
 426         *num_partitions = ARRAY_SIZE(phy3250_nand_partition);
 427         return phy3250_nand_partition;
 428 }
 429 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
 430 {
 431         .wdr_clks               = 3,
 432         .wwidth                 = 28571428,
 433         .whold                  = 100000000,
 434         .wsetup                 = 66666666,
 435         .rdr_clks               = 3,
 436         .rwidth                 = 28571428,
 437         .rhold                  = 100000000,
 438         .rsetup                 = 66666666,
 439         .use16bus               = 0,
 440         .enable_write_prot      = nandwp_enable,
 441         .partition_info         = phy3250_nand_partitions,
 442 };
 443
 444 /*
 445  * SLC NAND resources
 446  */
 447 static struct resource slc_nand_resources[] = {
 448         [0] = {
 449                 .start  = LPC32XX_SLC_BASE,
 450                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
 451                 .flags  = IORESOURCE_MEM,
 452         },
 453
 454         [1] = {
 455                 .start  = IRQ_LPC32XX_FLASH,
 456                 .end    = IRQ_LPC32XX_FLASH,
 457                 .flags  = IORESOURCE_IRQ,
 458         },
 459
 460 };
 461 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
 462 static struct platform_device lpc32xx_slc_nand_device = {
 463         .name           = "lpc32xx-nand",
 464         .id             = 0,
 465         .dev            = {
 466                                 .platform_data  = &lpc32xx_nandcfg,
 467                                 .dma_mask    = &lpc32xx_slc_dma_mask,
 468                                 .coherent_dma_mask = ~0UL,
 469         },
 470         .num_resources  = ARRAY_SIZE(slc_nand_resources),
 471         .resource       = slc_nand_resources,
 472 };
 473 #endif
 474
 475 /*
 476  * Network Support
 477  */
 478 static struct lpc_net_cfg lpc32xx_netdata =
 479 {
 480         .phy_irq        = -1,
 481         .phy_mask       = 0xFFFFFFF0,
 482 };
 483
 484 static struct resource net_resources[] = {
 485         [0] = {
 486                 .start  = LPC32XX_ETHERNET_BASE,
 487                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
 488                 .flags  = IORESOURCE_MEM,
 489         },
 490
 491         [1] = {
 492                 .start  = IRQ_LPC32XX_ETHERNET,
 493                 .end    = IRQ_LPC32XX_ETHERNET,
 494                 .flags  = IORESOURCE_IRQ,
 495         },
 496
 497 };
 498
 499 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
 500 static struct platform_device lpc32xx_net_device = {
 501         .name           = "lpc-net",
 502         .id             = 0,
 503         .dev            = {
 504                 .dma_mask = &lpc32xx_mac_dma_mask,
 505                 .coherent_dma_mask = 0xffffffffUL,
 506                 .platform_data  = &lpc32xx_netdata,
 507         },
 508         .num_resources  = ARRAY_SIZE(net_resources),
 509         .resource       = net_resources,
 510 };
 511
 512 static struct platform_device *phy3250_devs[] __initdata = {
 513         &lpc32xx_i2c0_device,
 514         &lpc32xx_i2c1_device,
 515         &lpc32xx_i2c2_device,
 516         &lpc32xx_watchdog_device,
 517         &lpc32xx_gpio_led_device,
 518         &lpc32xx_rtc_device,
 519         &lpc32xx_tsc_device,
 520         &lpc32xx_kscan_device,
 521         &lpc32xx_net_device,
 522 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
 523         &lpc32xx_slc_nand_device,
 524 #endif
 525 #if defined(CONFIG_USB_OHCI_HCD)
 526         &lpc32xx_ohci_device,
 527 #endif
 528 #if defined(CONFIG_USB_GADGET_LPC32XX)
 529         &lpc32xx_usbd_device,
 530 #endif
 531 };
 532
 533 static struct amba_device *amba_devs[] __initdata = {
 534         &lpc32xx_clcd_device,
 535         &lpc32xx_ssp0_device,
 536 #if defined(CONFIG_MMC_ARMMMCI)
 537         &lpc32xx_mmc_device,
 538 #endif
 539 };
 540
 541 /*
 542  * Board specific functions
 543  */
 544 static void __init phy3250_board_init(void)
 545 {
 546         u32 tmp;
 547         int i;
 548
 549         lpc32xx_gpio_init();
 550
 551         /* Register GPIOs used on this board */
 552         if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
 553                 printk(KERN_ERR "Error requesting gpio %u",
 554                                 SPI0_CS_GPIO);
 555         else if (gpio_direction_output(SPI0_CS_GPIO, 1))
 556                 printk(KERN_ERR "Error setting gpio %u to output",
 557                                 SPI0_CS_GPIO);
 558
 559         if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
 560                 printk(KERN_ERR "Error requesting gpio %u",
 561                                 MMC_PWR_ENABLE_GPIO);
 562         else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
 563                 printk(KERN_ERR "Error setting gpio %u to output",
 564                                 MMC_PWR_ENABLE_GPIO);
 565
 566         /* Setup network interface for RMII mode */
 567         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
 568         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
 569         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
 570         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
 571
 572         /* Setup SLC NAND controller muxing */
 573         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
 574                 LPC32XX_CLKPWR_NAND_CLK_CTRL);
 575
 576         /* Setup LCD muxing to RGB565 */
 577         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
 578                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
 579                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
 580         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
 581         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 582
 583         /* Set up I2C pull levels */
 584         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
 585         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
 586                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
 587         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
 588
 589         /* Disable IrDA pulsing support on UART6 */
 590         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
 591         tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
 592         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
 593
 594         /* Enable DMA for I2S1 channel */
 595         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
 596         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
 597         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
 598
 599         lpc32xx_serial_init();
 600
 601         /*
 602          * AMBA peripheral clocks need to be enabled prior to AMBA device
 603          * detection or a data fault will occur, so enable the clocks
 604          * here. However, we don't want to enable them if the peripheral
 605          * isn't included in the image
 606          */
 607 #if defined(CONFIG_MMC_ARMMMCI)
 608         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 609         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
 610         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 611 #endif
 612
 613 #ifdef CONFIG_FB_ARMCLCD
 614         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 615         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
 616                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 617 #endif
 618 #ifdef CONFIG_SPI_PL022
 619         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
 620         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
 621                 LPC32XX_CLKPWR_SSP_CLK_CTRL);
 622 #endif
 623
 624         platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
 625         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 626                 struct amba_device *d = amba_devs[i];
 627                 amba_device_register(d, &iomem_resource);
 628         }
 629
 630         /* Test clock needed for UDA1380 initial init */
 631         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
 632                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
 633                 LPC32XX_CLKPWR_TEST_CLK_SEL);
 634
 635         i2c_register_board_info(0, phy3250_i2c_board_info,
 636                 ARRAY_SIZE(phy3250_i2c_board_info));
 637 }
 638
 639 static int __init lpc32xx_display_uid(void)
 640 {
 641         u32 uid[4];
 642
 643         lpc32xx_get_uid(uid);
 644
 645         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
 646                 uid[3], uid[2], uid[1], uid[0]);
 647
 648         return 1;
 649 }
 650 arch_initcall(lpc32xx_display_uid);
 651
 652 /*
 653  * Example code for setting up the BTN1 button (on GPI3) for system
 654  * wakeup and IRQ support. This will allow the GPI3 input to wake
 655  * up the system on a low edge. Edge based interrupts won't be
 656  * registered in the interrupt controller when the system is asleep,
 657  * although they will be registered in the event manager. For this,
 658  * reason, a level based interrupt state is recommended for GPIOs when
 659  * using IRQ and wakeup from GPI edge state.
 660  *
 661  */
 662 #define BTN1_GPIO               LPC32XX_GPIO(LPC32XX_GPI_P3_GRP, 3)
 663 static irqreturn_t phy3250_btn1_irq(int irq, void *dev)
 664 {
 665         printk(KERN_INFO "GPIO IRQ!\n");
 666
 667         return IRQ_HANDLED;
 668 }
 669
 670 static int __init phy3250_button_setup(void)
 671 {
 672         int ret;
 673
 674         if (gpio_request(BTN1_GPIO, "Button 1")) {
 675                 printk(KERN_ERR "Error requesting gpio %u", BTN1_GPIO);
 676                 return 0;
 677         }
 678
 679         /*
 680          * Wakeup/irq on low edge - the wakeup state will use the same
 681          * state as the IRQ edge state.
 682          */
 683         set_irq_type(IRQ_LPC32XX_GPI_03, IRQ_TYPE_EDGE_FALLING);
 684         ret = request_irq(IRQ_LPC32XX_GPI_03, phy3250_btn1_irq,
 685                 IRQF_DISABLED, "gpio_btn1_irq", NULL);
 686         if (ret < 0) {
 687                 printk(KERN_ERR "Can't request interrupt\n");
 688                 return 0;
 689         }
 690
 691         enable_irq_wake(IRQ_LPC32XX_GPI_03);
 692
 693         return 1;
 694 }
 695 device_initcall(phy3250_button_setup);
 696
 697 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
 698         /* Maintainer: Kevin Wells, NXP Semiconductors */
 699         .phys_io        = LPC32XX_UART5_BASE,
 700         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
 701         .boot_params    = 0x80000100,
 702         .map_io         = lpc32xx_map_io,
 703         .init_irq       = lpc32xx_init_irq,
 704         .timer          = &lpc32xx_timer,
 705         .init_machine   = phy3250_board_init,
 706 MACHINE_END
 707
 708 /* For backwards compatibility with older bootloaders only */
 709 MACHINE_START(LPC3XXX, "Phytec 3250 board with the LPC3250 Microcontroller")
 710         /* Maintainer: Kevin Wells, NXP Semiconductors */
 711         .phys_io        = LPC32XX_UART5_BASE,
 712         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
 713         .boot_params    = 0x80000100,
 714         .map_io         = lpc32xx_map_io,
 715         .init_irq       = lpc32xx_init_irq,
 716         .timer          = &lpc32xx_timer,
 717         .init_machine   = phy3250_board_init,
 718 MACHINE_END