Various power management updates and enhancements
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / irq.c
1 /*
2  * arch/arm/mach-lpc32xx/irq.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/kobject.h>
26
27 #include <mach/irqs.h>
28 #include <mach/hardware.h>
29 #include <mach/platform.h>
30 #include "common.h"
31
32 /*
33  * Default value representing the Activation polarity of all internal
34  * interrupt sources
35  */
36 #define MIC_APR_DEFAULT         0x3FF0EFE0
37 #define SIC1_APR_DEFAULT        0xFBD27186
38 #define SIC2_APR_DEFAULT        0x801810C0
39
40 /*
41  * Default value representing the Activation Type of all internal
42  * interrupt sources. All are level sensitive.
43  */
44 #define MIC_ATR_DEFAULT         0x00000000
45 #define SIC1_ATR_DEFAULT        0x00026000
46 #define SIC2_ATR_DEFAULT        0x00000000
47
48 struct lpc32xx_event_group_regs {
49         void __iomem *enab_reg;
50         void __iomem *edge_reg;
51         void __iomem *maskstat_reg;
52         void __iomem *rawstat_reg;
53 };
54
55 static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
56         .enab_reg = LPC32XX_CLKPWR_INT_ER,
57         .edge_reg = LPC32XX_CLKPWR_INT_AP,
58         .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
59         .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
60 };
61
62 static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
63         .enab_reg = LPC32XX_CLKPWR_PIN_ER,
64         .edge_reg = LPC32XX_CLKPWR_PIN_AP,
65         .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
66         .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
67 };
68
69 struct lpc32xx_event_info {
70         const struct lpc32xx_event_group_regs *event_group;
71         u32 mask;
72 };
73
74 /*
75  * Maps an IRQ number to and event mask and register
76  * All IRQs are event based wakeup IRQs except the UARTs. The UART RX
77  * wakeup is based on the pin state, not the UART IRQ state.
78  */
79 static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
80         [IRQ_LPC32XX_GPI_08] = {
81                 .event_group = &lpc32xx_event_pin_regs,
82                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
83         },
84         [IRQ_LPC32XX_GPI_09] = {
85                 .event_group = &lpc32xx_event_pin_regs,
86                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
87         },
88         [IRQ_LPC32XX_GPI_19] = {
89                 .event_group = &lpc32xx_event_pin_regs,
90                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
91         },
92         [IRQ_LPC32XX_GPI_07] = {
93                 .event_group = &lpc32xx_event_pin_regs,
94                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
95         },
96         [IRQ_LPC32XX_GPI_00] = {
97                 .event_group = &lpc32xx_event_pin_regs,
98                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
99         },
100         [IRQ_LPC32XX_GPI_01] = {
101                 .event_group = &lpc32xx_event_pin_regs,
102                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
103         },
104         [IRQ_LPC32XX_GPI_02] = {
105                 .event_group = &lpc32xx_event_pin_regs,
106                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
107         },
108         [IRQ_LPC32XX_GPI_03] = {
109                 .event_group = &lpc32xx_event_pin_regs,
110                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
111         },
112         [IRQ_LPC32XX_GPI_04] = {
113                 .event_group = &lpc32xx_event_pin_regs,
114                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
115         },
116         [IRQ_LPC32XX_GPI_05] = {
117                 .event_group = &lpc32xx_event_pin_regs,
118                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
119         },
120         [IRQ_LPC32XX_GPI_06] = {
121                 .event_group = &lpc32xx_event_pin_regs,
122                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
123         },
124         [IRQ_LPC32XX_GPI_28] = {
125                 .event_group = &lpc32xx_event_pin_regs,
126                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
127         },
128         [IRQ_LPC32XX_GPIO_00] = {
129                 .event_group = &lpc32xx_event_int_regs,
130                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
131         },
132         [IRQ_LPC32XX_GPIO_01] = {
133                 .event_group = &lpc32xx_event_int_regs,
134                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
135         },
136         [IRQ_LPC32XX_GPIO_02] = {
137                 .event_group = &lpc32xx_event_int_regs,
138                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
139         },
140         [IRQ_LPC32XX_GPIO_03] = {
141                 .event_group = &lpc32xx_event_int_regs,
142                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
143         },
144         [IRQ_LPC32XX_GPIO_04] = {
145                 .event_group = &lpc32xx_event_int_regs,
146                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
147         },
148         [IRQ_LPC32XX_GPIO_05] = {
149                 .event_group = &lpc32xx_event_int_regs,
150                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
151         },
152         [IRQ_LPC32XX_KEY] = {
153                 .event_group = &lpc32xx_event_int_regs,
154                 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
155         },
156         [IRQ_LPC32XX_ETHERNET] = {
157                 .event_group = &lpc32xx_event_int_regs,
158                 .mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
159         },
160         [IRQ_LPC32XX_USB_OTG_ATX] = {
161                 .event_group = &lpc32xx_event_int_regs,
162                 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
163         },
164         [IRQ_LPC32XX_USB_HOST] = {
165                 .event_group = &lpc32xx_event_int_regs,
166                 .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
167         },
168         [IRQ_LPC32XX_RTC] = {
169                 .event_group = &lpc32xx_event_int_regs,
170                 .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
171         },
172         [IRQ_LPC32XX_MSTIMER] = {
173                 .event_group = &lpc32xx_event_int_regs,
174                 .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
175         },
176         [IRQ_LPC32XX_TS_AUX] = {
177                 .event_group = &lpc32xx_event_int_regs,
178                 .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
179         },
180         [IRQ_LPC32XX_TS_P] = {
181                 .event_group = &lpc32xx_event_int_regs,
182                 .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
183         },
184         [IRQ_LPC32XX_TS_IRQ] = {
185                 .event_group = &lpc32xx_event_int_regs,
186                 .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
187         },
188 };
189
190 static void get_controller(unsigned int irq, unsigned int *base,
191         unsigned int *irqbit)
192 {
193         if (irq < 32) {
194                 *base = LPC32XX_MIC_BASE;
195                 *irqbit = 1 << irq;
196         } else if (irq < 64) {
197                 *base = LPC32XX_SIC1_BASE;
198                 *irqbit = 1 << (irq - 32);
199         } else {
200                 *base = LPC32XX_SIC2_BASE;
201                 *irqbit = 1 << (irq - 64);
202         }
203 }
204
205 static void lpc32xx_mask_irq(unsigned int irq)
206 {
207         unsigned int reg, ctrl, mask;
208
209         get_controller(irq, &ctrl, &mask);
210
211         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
212         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
213 }
214
215 static void lpc32xx_unmask_irq(unsigned int irq)
216 {
217         unsigned int reg, ctrl, mask;
218
219         get_controller(irq, &ctrl, &mask);
220
221         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
222         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
223 }
224
225 static void lpc32xx_ack_irq(unsigned int irq)
226 {
227         unsigned int ctrl, mask;
228
229         get_controller(irq, &ctrl, &mask);
230
231         __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
232
233         /* Also need to clear pending wake event */
234         if (lpc32xx_events[irq].mask != 0)
235                 __raw_writel(lpc32xx_events[irq].mask,
236                         lpc32xx_events[irq].event_group->rawstat_reg);
237 }
238
239 static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
240         int use_edge)
241 {
242         unsigned int reg, ctrl, mask;
243
244         get_controller(irq, &ctrl, &mask);
245
246         /* Activation level, high or low */
247         reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
248         if (use_high_level)
249                 reg |= mask;
250         else
251                 reg &= ~mask;
252         __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
253
254         /* Activation type, edge or level */
255         reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
256         if (use_edge)
257                 reg |= mask;
258         else
259                 reg &= ~mask;
260         __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
261
262         /* Use same polarity for the wake events */
263         if (lpc32xx_events[irq].mask != 0) {
264                 reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
265
266                 if (use_high_level)
267                         reg |= lpc32xx_events[irq].mask;
268                 else
269                         reg &= ~lpc32xx_events[irq].mask;
270
271                 __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
272         }
273 }
274
275 static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
276 {
277         switch (type) {
278         case IRQ_TYPE_EDGE_RISING:
279                 /* Rising edge sensitive */
280                 __lpc32xx_set_irq_type(irq, 1, 1);
281                 break;
282
283         case IRQ_TYPE_EDGE_FALLING:
284                 /* Falling edge sensitive */
285                 __lpc32xx_set_irq_type(irq, 0, 1);
286                 break;
287
288         case IRQ_TYPE_LEVEL_LOW:
289                 /* Low level sensitive */
290                 __lpc32xx_set_irq_type(irq, 0, 0);
291                 break;
292
293         case IRQ_TYPE_LEVEL_HIGH:
294                 /* High level sensitive */
295                 __lpc32xx_set_irq_type(irq, 1, 0);
296                 break;
297
298         /* Other modes are not supported */
299         default:
300                 return -EINVAL;
301         }
302
303         return 0;
304 }
305
306 static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
307 {
308         unsigned long eventreg;
309
310         if (lpc32xx_events[irqno].mask != 0) {
311                 eventreg = __raw_readl(lpc32xx_events[irqno].
312                         event_group->enab_reg);
313
314                 if (state)
315                         eventreg |= lpc32xx_events[irqno].mask;
316                 else {
317                         eventreg &= ~lpc32xx_events[irqno].mask;
318
319                         /*
320                          * When disabling the wakeup, clear the latched
321                          * event
322                          */
323                         __raw_writel(lpc32xx_events[irqno].mask,
324                                 lpc32xx_events[irqno].
325                                 event_group->rawstat_reg);
326                 }
327
328                 __raw_writel(eventreg,
329                         lpc32xx_events[irqno].event_group->enab_reg);
330
331                 return 0;
332         }
333
334         return -ENODEV;
335 }
336
337 static void __init lpc32xx_set_default_mappings(unsigned int apr,
338         unsigned int atr, unsigned int offset)
339 {
340         unsigned int i;
341
342         /* Set activation levels for each interrupt */
343         i = 0;
344         while (i < 32) {
345                 __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
346                         ((atr >> i) & 0x1));
347                 i++;
348         }
349 }
350
351 static struct irq_chip lpc32xx_irq_chip = {
352         .ack = lpc32xx_ack_irq,
353         .mask = lpc32xx_mask_irq,
354         .unmask = lpc32xx_unmask_irq,
355         .set_type = lpc32xx_set_irq_type,
356         .set_wake = lpc32xx_irq_wake
357 };
358
359 static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
360 {
361         unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
362
363         while (ints != 0) {
364                 int irqno = fls(ints) - 1;
365
366                 ints &= ~(1 << irqno);
367
368                 generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
369         }
370 }
371
372 static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
373 {
374         unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
375
376         while (ints != 0) {
377                 int irqno = fls(ints) - 1;
378
379                 ints &= ~(1 << irqno);
380
381                 generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
382         }
383 }
384
385 void __init lpc32xx_init_irq(void)
386 {
387         unsigned int i;
388
389         /* Setup MIC */
390         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
391         __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
392         __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
393
394         /* Setup SIC1 */
395         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
396         __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
397         __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
398
399         /* Setup SIC2 */
400         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
401         __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
402         __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
403
404         /* Configure supported IRQ's */
405         for (i = 0; i < NR_IRQS; i++) {
406                 set_irq_chip(i, &lpc32xx_irq_chip);
407                 set_irq_handler(i, handle_level_irq);
408                 set_irq_flags(i, IRQF_VALID);
409         }
410
411         /* Set default mappings */
412         lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
413         lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
414         lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
415
416         /* mask all interrupts except SUBIRQ */
417         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
418         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
419         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
420
421         /* MIC SUBIRQx interrupts will route handling to the chain handlers */
422         set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
423         set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
424
425         /* Initially disable all wake events */
426         __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
427         __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
428         __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
429
430         /*
431          * Default wake activation polarities, all pin sources are low edge
432          * triggered
433          */
434         __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
435                 LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
436                 LPC32XX_CLKPWR_INTSRC_RTC_BIT,
437                 LPC32XX_CLKPWR_INT_AP);
438         __raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
439
440         /* Clear latched wake event states */
441         __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
442                 LPC32XX_CLKPWR_PIN_RS);
443         __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
444                 LPC32XX_CLKPWR_INT_RS);
445 }