arm: lpc2xx: PM fixes and enhancements
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / irq.c
1 /*
2  * arch/arm/mach-lpc32xx/irq.c
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #ifdef CONFIG_PM_DEBUG
20 #define DEBUG
21 #endif
22
23 #include <linux/pm.h>
24 #include <linux/suspend.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/kobject.h>
32
33 #include <mach/irqs.h>
34 #include <mach/hardware.h>
35 #include <mach/platform.h>
36 #include "common.h"
37
38 unsigned int wakeupirq = -1;
39
40 struct lpc32xx_event_group_regs {
41         void __iomem *enab_reg;
42         void __iomem *edge_reg;
43         void __iomem *maskstat_reg;
44         void __iomem *rawstat_reg;
45 };
46
47 static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
48         .enab_reg = LPC32XX_CLKPWR_INT_ER,
49         .edge_reg = LPC32XX_CLKPWR_INT_AP,
50         .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
51         .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
52 };
53
54 static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
55         .enab_reg = LPC32XX_CLKPWR_PIN_ER,
56         .edge_reg = LPC32XX_CLKPWR_PIN_AP,
57         .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
58         .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
59 };
60
61 struct lpc32xx_event_info {
62         const struct lpc32xx_event_group_regs *event_group;
63         u32 mask;
64 };
65
66 static const char *lpc32xx_irqname[NR_IRQS] = {
67         [IRQ_LPC32XX_GPI_08] = "GPI_08",
68         [IRQ_LPC32XX_GPI_09] = "GPI_09",
69         [IRQ_LPC32XX_GPI_19] = "GPI_19",
70         [IRQ_LPC32XX_GPI_07] = "GPI_07",
71         [IRQ_LPC32XX_GPI_00] = "GPI_00",
72         [IRQ_LPC32XX_GPI_01] = "GPI_01",
73         [IRQ_LPC32XX_GPI_02] = "GPI_02",
74         [IRQ_LPC32XX_GPI_03] = "GPI_03",
75         [IRQ_LPC32XX_GPI_04] = "GPI_04",
76         [IRQ_LPC32XX_GPI_05] = "GPI_05",
77         [IRQ_LPC32XX_GPI_06] = "GPI_06",
78         [IRQ_LPC32XX_GPI_28] = "GPI_28",
79         [IRQ_LPC32XX_UART_IIR1] = "Uart_1",
80         [IRQ_LPC32XX_UART_IIR2] = "Uart_2",
81         [IRQ_LPC32XX_UART_IIR3] = "Uart_3",
82         [IRQ_LPC32XX_UART_IIR4] = "Uart_4",
83         [IRQ_LPC32XX_UART_IIR5] = "Uart_5",
84         [IRQ_LPC32XX_UART_IIR6] = "Uart_6",
85         [IRQ_LPC32XX_UART_IIR7] = "Uart_7",
86         [IRQ_LPC32XX_GPIO_00] = "GPIO_00",
87         [IRQ_LPC32XX_GPIO_01] = "GPIO_01",
88         [IRQ_LPC32XX_GPIO_02] = "GPIO_02",
89         [IRQ_LPC32XX_GPIO_03] = "GPIO_03",
90         [IRQ_LPC32XX_GPIO_04] = "GPIO_04",
91         [IRQ_LPC32XX_GPIO_05] = "GPIO_05",
92         [IRQ_LPC32XX_ETHERNET]    = "Ethernet",
93         [IRQ_LPC32XX_KEY]         = "Keyboard",
94         [IRQ_LPC32XX_USB_OTG_ATX] = "USB_OTG",
95         [IRQ_LPC32XX_USB_HOST]    = "USB_Host",
96         [IRQ_LPC32XX_RTC]     = "RTC",
97         [IRQ_LPC32XX_MSTIMER] = "MS_Timer",
98         [IRQ_LPC32XX_TS_AUX]  = "TS_AUX",
99         [IRQ_LPC32XX_TS_P]    = "TS_P",
100         [IRQ_LPC32XX_TS_IRQ]  = "TS_IRQ",
101 };
102
103 /*
104  * Maps an IRQ number to and event mask and register
105  * All IRQs are event based wakeup IRQs except the UARTs. The UART RX
106  * wakeup is based on the pin state, not the UART IRQ state.
107  */
108 static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
109         [IRQ_LPC32XX_GPI_08] = {
110                 .event_group = &lpc32xx_event_pin_regs,
111                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
112         },
113         [IRQ_LPC32XX_GPI_09] = {
114                 .event_group = &lpc32xx_event_pin_regs,
115                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
116         },
117         [IRQ_LPC32XX_GPI_19] = {
118                 .event_group = &lpc32xx_event_pin_regs,
119                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
120         },
121         [IRQ_LPC32XX_GPI_07] = {
122                 .event_group = &lpc32xx_event_pin_regs,
123                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
124         },
125         [IRQ_LPC32XX_GPI_00] = {
126                 .event_group = &lpc32xx_event_pin_regs,
127                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
128         },
129         [IRQ_LPC32XX_GPI_01] = {
130                 .event_group = &lpc32xx_event_pin_regs,
131                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
132         },
133         [IRQ_LPC32XX_GPI_02] = {
134                 .event_group = &lpc32xx_event_pin_regs,
135                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
136         },
137         [IRQ_LPC32XX_GPI_03] = {
138                 .event_group = &lpc32xx_event_pin_regs,
139                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
140         },
141         [IRQ_LPC32XX_GPI_04] = {
142                 .event_group = &lpc32xx_event_pin_regs,
143                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
144         },
145         [IRQ_LPC32XX_GPI_05] = {
146                 .event_group = &lpc32xx_event_pin_regs,
147                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
148         },
149         [IRQ_LPC32XX_GPI_06] = {
150                 .event_group = &lpc32xx_event_pin_regs,
151                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
152         },
153         [IRQ_LPC32XX_GPI_28] = {
154                 .event_group = &lpc32xx_event_pin_regs,
155                 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
156         },
157   /* UART */
158         [IRQ_LPC32XX_UART_IIR1] = {
159                 .event_group = &lpc32xx_event_pin_regs,
160                 .mask = LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT,
161         },
162         [IRQ_LPC32XX_UART_IIR2] = {
163                 .event_group = &lpc32xx_event_pin_regs,
164                 .mask = LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT,
165         },
166         [IRQ_LPC32XX_UART_IIR3] = {
167                 .event_group = &lpc32xx_event_pin_regs,
168                 .mask = LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT,
169         },
170         [IRQ_LPC32XX_UART_IIR4] = {
171                 .event_group = &lpc32xx_event_pin_regs,
172                 .mask = LPC32XX_CLKPWR_EXTSRC_U4_RX_BIT,
173         },
174         [IRQ_LPC32XX_UART_IIR5] = {
175                 .event_group = &lpc32xx_event_pin_regs,
176                 .mask = LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT,
177         },
178         [IRQ_LPC32XX_UART_IIR6] = {
179                 .event_group = &lpc32xx_event_pin_regs,
180                 .mask = LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT,
181         },
182         [IRQ_LPC32XX_UART_IIR7] = {
183                 .event_group = &lpc32xx_event_pin_regs,
184                 .mask = LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT,
185         },
186         [IRQ_LPC32XX_GPIO_00] = {
187                 .event_group = &lpc32xx_event_int_regs,
188                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
189         },
190         [IRQ_LPC32XX_GPIO_01] = {
191                 .event_group = &lpc32xx_event_int_regs,
192                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
193         },
194         [IRQ_LPC32XX_GPIO_02] = {
195                 .event_group = &lpc32xx_event_int_regs,
196                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
197         },
198         [IRQ_LPC32XX_GPIO_03] = {
199                 .event_group = &lpc32xx_event_int_regs,
200                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
201         },
202         [IRQ_LPC32XX_GPIO_04] = {
203                 .event_group = &lpc32xx_event_int_regs,
204                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
205         },
206         [IRQ_LPC32XX_GPIO_05] = {
207                 .event_group = &lpc32xx_event_int_regs,
208                 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
209         },
210         [IRQ_LPC32XX_KEY] = {
211                 .event_group = &lpc32xx_event_int_regs,
212                 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
213         },
214         [IRQ_LPC32XX_ETHERNET] = {
215                 .event_group = &lpc32xx_event_int_regs,
216                 .mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
217         },
218         [IRQ_LPC32XX_USB_OTG_ATX] = {
219                 .event_group = &lpc32xx_event_int_regs,
220                 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
221         },
222         [IRQ_LPC32XX_USB_HOST] = {
223                 .event_group = &lpc32xx_event_int_regs,
224                 .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
225         },
226         [IRQ_LPC32XX_RTC] = {
227                 .event_group = &lpc32xx_event_int_regs,
228                 .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
229         },
230         [IRQ_LPC32XX_MSTIMER] = {
231                 .event_group = &lpc32xx_event_int_regs,
232                 .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
233         },
234         [IRQ_LPC32XX_TS_AUX] = {
235                 .event_group = &lpc32xx_event_int_regs,
236                 .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
237         },
238         [IRQ_LPC32XX_TS_P] = {
239                 .event_group = &lpc32xx_event_int_regs,
240                 .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
241         },
242         [IRQ_LPC32XX_TS_IRQ] = {
243                 .event_group = &lpc32xx_event_int_regs,
244                 .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
245         },
246 };
247
248 static void get_controller(unsigned int irq, unsigned int *base,
249         unsigned int *irqbit)
250 {
251         if (irq < 32) {
252                 *base = LPC32XX_MIC_BASE;
253                 *irqbit = 1 << irq;
254         } else if (irq < 64) {
255                 *base = LPC32XX_SIC1_BASE;
256                 *irqbit = 1 << (irq - 32);
257         } else {
258                 *base = LPC32XX_SIC2_BASE;
259                 *irqbit = 1 << (irq - 64);
260         }
261 }
262
263 static void lpc32xx_mask_irq(unsigned int irq)
264 {
265         unsigned int reg, ctrl, mask;
266
267         get_controller(irq, &ctrl, &mask);
268
269         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
270         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
271 }
272
273 static void lpc32xx_unmask_irq(unsigned int irq)
274 {
275         unsigned int reg, ctrl, mask;
276
277         get_controller(irq, &ctrl, &mask);
278
279         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
280         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
281 }
282
283 static void lpc32xx_ack_irq(unsigned int irq)
284 {
285         unsigned int ctrl, mask;
286
287         get_controller(irq, &ctrl, &mask);
288
289         __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
290
291         /* Also need to clear pending wake event */
292         if (lpc32xx_events[irq].mask != 0)
293                 __raw_writel(lpc32xx_events[irq].mask,
294                         lpc32xx_events[irq].event_group->rawstat_reg);
295 }
296
297 static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
298         int use_edge)
299 {
300         unsigned int reg, ctrl, mask;
301
302         get_controller(irq, &ctrl, &mask);
303
304         /* Activation level, high or low */
305         reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
306         if (use_high_level)
307                 reg |= mask;
308         else
309                 reg &= ~mask;
310         __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
311
312         /* Activation type, edge or level */
313         reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
314         if (use_edge)
315                 reg |= mask;
316         else
317                 reg &= ~mask;
318         __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
319
320         /* Use same polarity for the wake events */
321         if (lpc32xx_events[irq].mask != 0) {
322                 reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
323
324                 if (use_high_level)
325                         reg |= lpc32xx_events[irq].mask;
326                 else
327                         reg &= ~lpc32xx_events[irq].mask;
328
329                 __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
330         }
331 }
332
333 static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
334 {
335         switch (type) {
336         case IRQ_TYPE_EDGE_RISING:
337                 /* Rising edge sensitive */
338                 __lpc32xx_set_irq_type(irq, 1, 1);
339                 break;
340
341         case IRQ_TYPE_EDGE_FALLING:
342                 /* Falling edge sensitive */
343                 __lpc32xx_set_irq_type(irq, 0, 1);
344                 break;
345
346         case IRQ_TYPE_LEVEL_LOW:
347                 /* Low level sensitive */
348                 __lpc32xx_set_irq_type(irq, 0, 0);
349                 break;
350
351         case IRQ_TYPE_LEVEL_HIGH:
352                 /* High level sensitive */
353                 __lpc32xx_set_irq_type(irq, 1, 0);
354                 break;
355
356         /* Other modes are not supported */
357         default:
358                 return -EINVAL;
359         }
360
361         return 0;
362 }
363
364 #ifdef CONFIG_PM
365 static u32 backup_irqs[NR_IRQ_CTRLS];
366 static u32 wakeup_irqs[NR_IRQ_CTRLS];
367
368 static ssize_t wakeup_event_show(struct kobject *kobj,
369                 struct kobj_attribute *attr, char *buf)
370 {
371         if(wakeupirq < 0) {
372                 return 0;
373         }
374
375         return sprintf(buf, "%s\n", lpc32xx_irqname[wakeupirq]);
376 }
377 static struct kobj_attribute wakeup_event_attr =
378                         __ATTR(wakeup_event, 0644, wakeup_event_show, NULL);
379 #endif
380
381 void lpc32xx_irq_suspend(suspend_state_t state)
382 {
383 #ifdef CONFIG_PM
384         unsigned int i, ctrl, mask;
385
386         for( i=0; i < NR_IRQ_CTRLS; i++) {
387                 get_controller((i*32), &ctrl, &mask);
388
389                 /* Backup programmed IRQs */
390                 backup_irqs[i] = __raw_readl(LPC32XX_INTC_MASK(ctrl));
391
392                 /* Disable all interrupts */
393                 __raw_writel(0, LPC32XX_INTC_MASK(ctrl));
394
395                 if(state == PM_SUSPEND_STANDBY) {
396                         pr_debug("Wakeup_irq[%d] = 0x%08X\n", i, wakeup_irqs[i] );
397
398                         /* Program interrupts only in standby because of DDR wakeup issues*/
399                         __raw_writel( wakeup_irqs[i], LPC32XX_INTC_RAW_STAT(ctrl));
400                         __raw_writel( wakeup_irqs[i], LPC32XX_INTC_MASK(ctrl));
401                 }
402         }
403
404         if(state == PM_SUSPEND_MEM)     {
405                 pr_debug("Start_enable_pin = 0x%X\n",
406                                 __raw_readl(lpc32xx_event_pin_regs.enab_reg));
407                 pr_debug("Start_enable_internal = 0x%X\n",
408                                 __raw_readl(lpc32xx_event_int_regs.enab_reg));
409         }
410
411         /* Clear Raw Status registers */
412         __raw_writel(LPC32XX_CLKPWR_EXTSRC_MASK,
413                         lpc32xx_event_pin_regs.rawstat_reg);
414         __raw_writel(LPC32XX_CLKPWR_INTSRC_MASK,
415                         lpc32xx_event_int_regs.rawstat_reg);
416
417         sysfs_remove_file(power_kobj, &wakeup_event_attr.attr);
418 #endif
419 }
420
421 void lpc32xx_irq_resume(suspend_state_t state)
422 {
423 #ifdef CONFIG_PM
424         unsigned int i, ctrl, mask;
425         unsigned int pinRegMask, intRegMask;
426         unsigned int statusReg = 0;
427
428         pinRegMask = __raw_readl(lpc32xx_event_pin_regs.maskstat_reg);
429         intRegMask = __raw_readl(lpc32xx_event_int_regs.maskstat_reg);
430         pr_debug("Pin Register wakeup mask = 0x%X\n", pinRegMask);
431         pr_debug("Int Register wakeup mask = 0x%X\n", intRegMask);
432
433         /* Scan all lpc32xx_events to find who woke up */
434         for(i=0; i< NR_IRQS; i++) {
435                 /* Check IRQ can be defined as wakeup IRQ */
436                 if (lpc32xx_events[i].mask != 0) {
437                         pr_debug("Scan IRQ %d\n",i);
438                         if((lpc32xx_events[i].event_group->enab_reg == lpc32xx_event_pin_regs.enab_reg)
439                                         && pinRegMask) {
440                                 pr_debug("Test mask 0x%X\n",lpc32xx_events[i].mask);
441                                 if(lpc32xx_events[i].mask == pinRegMask) {
442                                         wakeupirq = i;
443                                         break;
444                                 }
445                         }
446
447                         if((lpc32xx_events[i].event_group->enab_reg == lpc32xx_event_int_regs.enab_reg)
448                                         && intRegMask) {
449                                 pr_debug("Test mask 0x%X\n",lpc32xx_events[i].mask);
450                                 if(lpc32xx_events[i].mask == intRegMask) {
451                                         wakeupirq = i;
452                                         break;
453                                 }
454                         }
455                 }
456         }
457
458         /* Clear Raw Status registers */
459         __raw_writel(LPC32XX_CLKPWR_EXTSRC_MASK,
460                         lpc32xx_event_pin_regs.rawstat_reg);
461         __raw_writel(LPC32XX_CLKPWR_INTSRC_MASK,
462                         lpc32xx_event_int_regs.rawstat_reg);
463
464         for( i=0; i < NR_IRQ_CTRLS; i++) {
465                 get_controller( (i*32), &ctrl, &mask);
466
467                 statusReg = __raw_readl(LPC32XX_INTC_STAT(ctrl));
468
469                 pr_debug("statusReg %d = 0x%08X\n",i,statusReg);
470
471                 /* Disable all interrupts */
472                 __raw_writel( 0, LPC32XX_INTC_MASK(ctrl));
473
474                 /* Clear Wakeup pending interrupts */
475                 __raw_writel(wakeup_irqs[i], LPC32XX_INTC_RAW_STAT(ctrl));
476
477                 /* Restore old controller config */
478                 __raw_writel(backup_irqs[i], LPC32XX_INTC_MASK(ctrl));
479         }
480
481         if(wakeupirq > 0) {
482                 pr_debug("Wakeup source: %s\n", lpc32xx_irqname[wakeupirq]);
483                 sysfs_create_file(power_kobj, &wakeup_event_attr.attr);
484         }
485 #endif
486 }
487
488 static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
489 {
490         unsigned long eventreg;
491         unsigned int ctrl_nr, ctrl, mask;
492
493         if (unlikely(irqno >= (32 * NR_IRQ_CTRLS))) {
494                 return -EINVAL;
495         }
496
497         get_controller(irqno, &ctrl, &mask);
498         ctrl_nr = irqno / 32;
499
500 #ifdef CONFIG_PM_DEBUG
501         if (state) {
502                 pr_debug("Set irq %d as wakeup IRQ\n", irqno);
503                 wakeup_irqs[ctrl_nr] |= mask;
504                 if( ctrl_nr == 1 ) {
505                         wakeup_irqs[0] |= ( 1<<IRQ_LPC32XX_SUB1IRQ );
506                 }
507                 if( ctrl_nr == 2 ) {
508                         wakeup_irqs[0] |= ( 1<<IRQ_LPC32XX_SUB2IRQ );
509                 }
510         }
511         else
512         {
513                 pr_debug("Disable wakeup from irq %d \n", irqno);
514                 wakeup_irqs[ctrl_nr] &= ~mask;
515                 if( (ctrl_nr == 1) && (wakeup_irqs[1] == 0) )
516                         wakeup_irqs[0] &= ~( 1<<IRQ_LPC32XX_SUB1IRQ );
517                 if( (ctrl_nr == 2) && (wakeup_irqs[2] == 0) )
518                                 wakeup_irqs[0] &= ~( 1<<IRQ_LPC32XX_SUB2IRQ );
519         }
520 #endif
521
522         if ( lpc32xx_events[irqno].mask == 0 ) {
523                 pr_warning("Can't configure irq %d as wakeup source\n",irqno);
524                 return 0;
525         }
526
527         if (lpc32xx_events[irqno].mask != 0) {
528                 eventreg = __raw_readl(lpc32xx_events[irqno].
529                         event_group->enab_reg);
530
531                 if (state)
532                         eventreg |= lpc32xx_events[irqno].mask;
533                 else {
534                         eventreg &= ~lpc32xx_events[irqno].mask;
535
536                         /*
537                          * When disabling the wakeup, clear the latched
538                          * event
539                          */
540                         __raw_writel(lpc32xx_events[irqno].mask,
541                                 lpc32xx_events[irqno].
542                                 event_group->rawstat_reg);
543                 }
544
545                 __raw_writel(eventreg,
546                         lpc32xx_events[irqno].event_group->enab_reg);
547
548                 return 0;
549         }
550
551         __raw_writel(lpc32xx_events[irqno].mask,
552                 lpc32xx_events[irqno].event_group->rawstat_reg);
553
554         return -ENODEV;
555 }
556
557 static void __init lpc32xx_set_default_mappings(unsigned int apr,
558         unsigned int atr, unsigned int offset)
559 {
560         unsigned int i;
561
562         /* Set activation levels for each interrupt */
563         i = 0;
564         while (i < 32) {
565                 __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
566                         ((atr >> i) & 0x1));
567                 i++;
568         }
569 }
570
571 static struct irq_chip lpc32xx_irq_chip = {
572         .ack = lpc32xx_ack_irq,
573         .mask = lpc32xx_mask_irq,
574         .unmask = lpc32xx_unmask_irq,
575         .set_type = lpc32xx_set_irq_type,
576         .set_wake = lpc32xx_irq_wake
577 };
578
579 static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
580 {
581         unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
582
583         while (ints != 0) {
584                 int irqno = fls(ints) - 1;
585
586                 ints &= ~(1 << irqno);
587
588                 generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
589         }
590 }
591
592 static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
593 {
594         unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
595
596         while (ints != 0) {
597                 int irqno = fls(ints) - 1;
598
599                 ints &= ~(1 << irqno);
600
601                 generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
602         }
603 }
604
605 void __init lpc32xx_init_irq(void)
606 {
607         unsigned int i;
608
609         /* Setup MIC */
610         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
611         __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
612         __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
613
614         /* Setup SIC1 */
615         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
616         __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
617         __raw_writel(SIC1_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
618
619         /* Setup SIC2 */
620         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
621         __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
622         __raw_writel(SIC2_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
623
624         /* Configure supported IRQ's */
625         for (i = 0; i < NR_IRQS; i++) {
626                 set_irq_chip(i, &lpc32xx_irq_chip);
627                 set_irq_handler(i, handle_level_irq);
628                 set_irq_flags(i, IRQF_VALID);
629         }
630
631         /* Set default mappings */
632         lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
633         lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
634         lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
635
636         /* mask all interrupts except SUBIRQ */
637         __raw_writel((1 << IRQ_LPC32XX_SUB1IRQ) | (1 << IRQ_LPC32XX_SUB2IRQ) |
638                         (1 << IRQ_LPC32XX_SUB1FIQ) | (1 << IRQ_LPC32XX_SUB2FIQ),
639                         LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
640         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
641         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
642
643         /* MIC SUBIRQx interrupts will route handling to the chain handlers */
644         set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
645         set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
646
647         /* Initially disable all wake events */
648         __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
649         __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
650         __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
651
652         /* Clear latched wake event states */
653         __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
654                 LPC32XX_CLKPWR_PIN_RS);
655         __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
656                 LPC32XX_CLKPWR_INT_RS);
657 }