arm: lpc2xx: PM fixes and enhancements
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / include / mach / irqs.h
1 /*
2  * arch/arm/mach-lpc32xx/include/mach/irqs.h
3  *
4  * Author: Kevin Wells <kevin.wells@nxp.com>
5  *
6  * Copyright (C) 2010 NXP Semiconductors
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #ifndef __ASM_ARM_ARCH_IRQS_H
20 #define __ASM_ARM_ARCH_IRQS_H
21
22 #define LPC32XX_SIC1_IRQ(n)             (32 + (n))
23 #define LPC32XX_SIC2_IRQ(n)             (64 + (n))
24
25 /*
26  * Default value representing the Activation polarity of all internal
27  * interrupt sources
28  */
29 #define MIC_APR_DEFAULT         0x3FF0EFE0
30 #define SIC1_APR_DEFAULT        0xFBD27186
31 #define SIC2_APR_DEFAULT        0x801810C0
32
33 /*
34  * Default value representing the Activation Type of all internal
35  * interrupt sources. All are level sensitive.
36  */
37 #define MIC_ATR_DEFAULT         0x00000000
38 #define SIC1_ATR_DEFAULT        0x00026000
39 #define SIC2_ATR_DEFAULT        0x00000000
40
41 /*
42  * MIC interrupts
43  */
44 #define IRQ_LPC32XX_SUB1IRQ             0
45 #define IRQ_LPC32XX_SUB2IRQ             1
46 #define IRQ_LPC32XX_PWM3                3
47 #define IRQ_LPC32XX_PWM4                4
48 #define IRQ_LPC32XX_HSTIMER             5
49 #define IRQ_LPC32XX_WATCH               6
50 #define IRQ_LPC32XX_UART_IIR3           7
51 #define IRQ_LPC32XX_UART_IIR4           8
52 #define IRQ_LPC32XX_UART_IIR5           9
53 #define IRQ_LPC32XX_UART_IIR6           10
54 #define IRQ_LPC32XX_FLASH               11
55 #define IRQ_LPC32XX_SD1                 13
56 #define IRQ_LPC32XX_LCD                 14
57 #define IRQ_LPC32XX_SD0                 15
58 #define IRQ_LPC32XX_TIMER0              16
59 #define IRQ_LPC32XX_TIMER1              17
60 #define IRQ_LPC32XX_TIMER2              18
61 #define IRQ_LPC32XX_TIMER3              19
62 #define IRQ_LPC32XX_SSP0                20
63 #define IRQ_LPC32XX_SSP1                21
64 #define IRQ_LPC32XX_I2S0                22
65 #define IRQ_LPC32XX_I2S1                23
66 #define IRQ_LPC32XX_UART_IIR7           24
67 #define IRQ_LPC32XX_UART_IIR2           25
68 #define IRQ_LPC32XX_UART_IIR1           26
69 #define IRQ_LPC32XX_MSTIMER             27
70 #define IRQ_LPC32XX_DMA                 28
71 #define IRQ_LPC32XX_ETHERNET            29
72 #define IRQ_LPC32XX_SUB1FIQ             30
73 #define IRQ_LPC32XX_SUB2FIQ             31
74
75 /*
76  * SIC1 interrupts start at offset 32
77  */
78 #define IRQ_LPC32XX_JTAG_COMM_TX        LPC32XX_SIC1_IRQ(1)
79 #define IRQ_LPC32XX_JTAG_COMM_RX        LPC32XX_SIC1_IRQ(2)
80 #define IRQ_LPC32XX_GPI_28              LPC32XX_SIC1_IRQ(4)
81 #define IRQ_LPC32XX_TS_P                LPC32XX_SIC1_IRQ(6)
82 #define IRQ_LPC32XX_TS_IRQ              LPC32XX_SIC1_IRQ(7)
83 #define IRQ_LPC32XX_TS_AUX              LPC32XX_SIC1_IRQ(8)
84 #define IRQ_LPC32XX_SPI2                LPC32XX_SIC1_IRQ(12)
85 #define IRQ_LPC32XX_PLLUSB              LPC32XX_SIC1_IRQ(13)
86 #define IRQ_LPC32XX_PLLHCLK             LPC32XX_SIC1_IRQ(14)
87 #define IRQ_LPC32XX_PLL397              LPC32XX_SIC1_IRQ(17)
88 #define IRQ_LPC32XX_I2C_2               LPC32XX_SIC1_IRQ(18)
89 #define IRQ_LPC32XX_I2C_1               LPC32XX_SIC1_IRQ(19)
90 #define IRQ_LPC32XX_RTC                 LPC32XX_SIC1_IRQ(20)
91 #define IRQ_LPC32XX_KEY                 LPC32XX_SIC1_IRQ(22)
92 #define IRQ_LPC32XX_SPI1                LPC32XX_SIC1_IRQ(23)
93 #define IRQ_LPC32XX_SW                  LPC32XX_SIC1_IRQ(24)
94 #define IRQ_LPC32XX_USB_OTG_TIMER       LPC32XX_SIC1_IRQ(25)
95 #define IRQ_LPC32XX_USB_OTG_ATX         LPC32XX_SIC1_IRQ(26)
96 #define IRQ_LPC32XX_USB_HOST            LPC32XX_SIC1_IRQ(27)
97 #define IRQ_LPC32XX_USB_DEV_DMA         LPC32XX_SIC1_IRQ(28)
98 #define IRQ_LPC32XX_USB_DEV_LP          LPC32XX_SIC1_IRQ(29)
99 #define IRQ_LPC32XX_USB_DEV_HP          LPC32XX_SIC1_IRQ(30)
100 #define IRQ_LPC32XX_USB_I2C             LPC32XX_SIC1_IRQ(31)
101
102 /*
103  * SIC2 interrupts start at offset 64
104  */
105 #define IRQ_LPC32XX_GPIO_00             LPC32XX_SIC2_IRQ(0)
106 #define IRQ_LPC32XX_GPIO_01             LPC32XX_SIC2_IRQ(1)
107 #define IRQ_LPC32XX_GPIO_02             LPC32XX_SIC2_IRQ(2)
108 #define IRQ_LPC32XX_GPIO_03             LPC32XX_SIC2_IRQ(3)
109 #define IRQ_LPC32XX_GPIO_04             LPC32XX_SIC2_IRQ(4)
110 #define IRQ_LPC32XX_GPIO_05             LPC32XX_SIC2_IRQ(5)
111 #define IRQ_LPC32XX_SPI2_DATAIN         LPC32XX_SIC2_IRQ(6)
112 #define IRQ_LPC32XX_U2_HCTS             LPC32XX_SIC2_IRQ(7)
113 #define IRQ_LPC32XX_P0_P1_IRQ           LPC32XX_SIC2_IRQ(8)
114 #define IRQ_LPC32XX_GPI_08              LPC32XX_SIC2_IRQ(9)
115 #define IRQ_LPC32XX_GPI_09              LPC32XX_SIC2_IRQ(10)
116 #define IRQ_LPC32XX_GPI_19              LPC32XX_SIC2_IRQ(11)
117 #define IRQ_LPC32XX_U7_HCTS             LPC32XX_SIC2_IRQ(12)
118 #define IRQ_LPC32XX_GPI_07              LPC32XX_SIC2_IRQ(15)
119 #define IRQ_LPC32XX_SDIO                LPC32XX_SIC2_IRQ(18)
120 #define IRQ_LPC32XX_U5_RX               LPC32XX_SIC2_IRQ(19)
121 #define IRQ_LPC32XX_SPI1_DATAIN         LPC32XX_SIC2_IRQ(20)
122 #define IRQ_LPC32XX_GPI_00              LPC32XX_SIC2_IRQ(22)
123 #define IRQ_LPC32XX_GPI_01              LPC32XX_SIC2_IRQ(23)
124 #define IRQ_LPC32XX_GPI_02              LPC32XX_SIC2_IRQ(24)
125 #define IRQ_LPC32XX_GPI_03              LPC32XX_SIC2_IRQ(25)
126 #define IRQ_LPC32XX_GPI_04              LPC32XX_SIC2_IRQ(26)
127 #define IRQ_LPC32XX_GPI_05              LPC32XX_SIC2_IRQ(27)
128 #define IRQ_LPC32XX_GPI_06              LPC32XX_SIC2_IRQ(28)
129 #define IRQ_LPC32XX_SYSCLK              LPC32XX_SIC2_IRQ(31)
130
131 #define NR_IRQS                         96
132 #define NR_IRQ_CTRLS    3
133
134 #endif