arm:lpc32xx:spi/pl022 Add spi->mode support AMBA SPI driver
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / fdi3250.c
1 /*
2  * arch/arm/mach-lpc32xx/fdi3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/gpio.h>
29 #include <linux/input.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl022.h>
33 #include <linux/amba/mmci.h>
34
35 #include <asm/setup.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38
39 #include <mach/hardware.h>
40 #include <mach/platform.h>
41 #include <mach/board.h>
42 #include "common.h"
43
44 /*
45  * Mapped GPIOLIB GPIOs
46  */
47 #define LED_GPIO                LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 3)
48 #define SPI_CS_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
49 #define NAND_WP_GPIO            LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
50
51 /*
52  * Tick LED
53  */
54 static struct gpio_led phy_leds[] = {
55         {
56                 .name                   = "led0",
57                 .gpio                   = LED_GPIO,
58                 .active_low             = 1,
59                 .default_trigger        = "heartbeat",
60         },
61 };
62
63 static struct gpio_led_platform_data led_data = {
64         .leds = phy_leds,
65         .num_leds = ARRAY_SIZE(phy_leds),
66 };
67
68 static struct platform_device lpc32xx_gpio_led_device = {
69         .name                   = "leds-gpio",
70         .id                     = -1,
71         .dev.platform_data      = &led_data,
72 };
73
74 /*
75  * AMBA SSP (SPI)
76  */
77 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
78         .bus_id                 = 0,
79         .num_chipselect         = 2,
80         .enable_dma             = 0,
81 };
82
83 static struct amba_device lpc32xx_ssp0_device = {
84         .dev    = {
85                 .coherent_dma_mask      = ~0,
86                 .init_name              = "dev:ssp0",
87                 .platform_data          = &lpc32xx_ssp0_data,
88         },
89         .res                            = {
90                 .start                  = LPC32XX_SSP0_BASE,
91                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
92                 .flags                  = IORESOURCE_MEM,
93         },
94         .dma_mask                       = ~0,
95         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
96 };
97
98 /* SPIDEV chip select function */
99 static void fdi3250_spi_cs_set(u32 control)
100 {
101         gpio_set_value(SPI_CS_GPIO, (int) control);
102 }
103
104 /* SPIDEV parameters */
105 static struct pl022_config_chip spi0_chip_info = {
106         .com_mode               = INTERRUPT_TRANSFER,
107         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
108         .hierarchy              = SSP_MASTER,
109         .slave_tx_disable       = 0,
110         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
111         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
112         .ctrl_len               = SSP_BITS_8,
113         .wait_state             = SSP_MWIRE_WAIT_ZERO,
114         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
115         .cs_control             = fdi3250_spi_cs_set,
116 };
117
118 /* SPI devices registration */
119 static int __init fdi3250_spi_devices_register(void)
120 {
121         static struct spi_board_info info[] = {
122                 {
123                         .modalias = "spidev",
124                         .max_speed_hz = 2500000,
125                         .bus_num = 0,
126                         .chip_select = 0,
127                         .controller_data = &spi0_chip_info,
128                 },
129         };
130
131         return spi_register_board_info(info, ARRAY_SIZE(info));
132 }
133 arch_initcall(fdi3250_spi_devices_register);
134
135 #if defined (CONFIG_FB_ARMCLCD)
136 /*
137  * Board specific LCD setup and functions
138  */
139 #if defined (CONFIG_SOM9DIMM3250_LCD_PANEL)
140 /*
141  * Support for QVGA portrait panel
142  */
143 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
144 static struct clcd_panel conn_lcd_panel = {
145         .mode           = {
146                 .name           = "QVGA portrait",
147                 .refresh        = 30,
148                 .xres           = 320,
149                 .yres           = 240,
150                 .pixclock       = 158730,
151                 .left_margin    = 11,
152                 .right_margin   = 3,
153                 .upper_margin   = 7,
154                 .lower_margin   = 7,
155                 .hsync_len      = 69,
156                 .vsync_len      = 45,
157                 .sync           = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
158                 .vmode          = FB_VMODE_NONINTERLACED,
159         },
160         .width          = -1,
161         .height         = -1,
162         .tim2           = 0,
163         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
164                                 CNTL_LCDBPP16_565),
165         .bpp            = 16,
166 };
167 #define PANEL_SIZE (3 * SZ_64K)
168 #endif
169 #if defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
170 static struct clcd_panel conn_lcd_panel = {
171         .mode           = {
172                 .name           = "VGA portrait",
173                 .refresh        = 30,
174                 .xres           = 640,
175                 .yres           = 480,
176                 .pixclock       = 41666,
177                 .left_margin    = 10,
178                 .right_margin   = 120,
179                 .upper_margin   = 7,
180                 .lower_margin   = 35,
181                 .hsync_len      = 30,
182                 .vsync_len      = 3,
183                 .sync           = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
184                 .vmode          = FB_VMODE_NONINTERLACED,
185         },
186         .width          = -1,
187         .height         = -1,
188         .tim2           = 0,
189         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
190                                 CNTL_LCDBPP16_565),
191         .bpp            = 16,
192 };
193 #define PANEL_SIZE (10 * SZ_64K)
194 #endif
195
196 #endif // CONFIG_SOM9DIMM3250_LCD_PANEL
197
198 #if defined (CONFIG_MMC_ARMMMCI)
199 static u32 mmc_translate_vdd(struct device *dev, unsigned int vdd)
200 {
201         return 0;
202 }
203
204 unsigned int fdi_mmc_status_always_on(struct device *dev)
205 {
206         return 0;
207 }
208 /*
209  * Board specific MMC driver data
210  */
211 struct mmci_platform_data lpc32xx_plat_data = {
212         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
213         .translate_vdd  = mmc_translate_vdd,
214         .capabilities   = MMC_CAP_4_BIT_DATA,
215         .gpio_wp        = ARCH_NR_GPIOS + 1,
216         .gpio_cd        = ARCH_NR_GPIOS + 1,
217         .status         = fdi_mmc_status_always_on,
218 };
219
220 /*
221  * SD card controller resources
222  */
223 struct amba_device lpc32xx_mmc_device = {
224         .dev = {
225                 .coherent_dma_mask      = ~0,
226                 .init_name                 = "dev:mmc0",
227                 .platform_data          = &lpc32xx_plat_data,
228         },
229         .res = {
230                 .start                  = LPC32XX_SD_BASE,
231                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
232                 .flags                  = IORESOURCE_MEM,
233         },
234         .dma_mask                       = ~0,
235         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
236 };
237 #endif
238
239 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
240 {
241         dma_addr_t dma;
242
243         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
244                         PANEL_SIZE, &dma, GFP_KERNEL);
245         if (!fb->fb.screen_base) {
246                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
247                 return -ENOMEM;
248         }
249
250         fb->fb.fix.smem_start = dma;
251         fb->fb.fix.smem_len = PANEL_SIZE;
252         fb->panel = &conn_lcd_panel;
253
254         return 0;
255 }
256
257 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
258 {
259         return dma_mmap_writecombine(&fb->dev->dev, vma,
260                                      fb->fb.screen_base,
261                                      fb->fb.fix.smem_start,
262                                      fb->fb.fix.smem_len);
263 }
264
265 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
266 {
267         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
268                               fb->fb.screen_base, fb->fb.fix.smem_start);
269 }
270
271 void clcd_disable(struct clcd_fb *fb)
272 {
273 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
274         __raw_writel(0x40000000, io_p2v(LPC32XX_PWM1_BASE));
275 #elif defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
276         __raw_writel(0x00000000, io_p2v(LPC32XX_PWM1_BASE));
277 #endif
278 }
279
280 void clcd_enable(struct clcd_fb *fb)
281 {
282 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
283         __raw_writel(0x00000000, io_p2v(LPC32XX_PWM1_BASE));
284 #elif defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
285         __raw_writel(0x40000000, io_p2v(LPC32XX_PWM1_BASE));
286 #endif
287 }
288
289 struct clcd_board lpc32xx_clcd_data = {
290 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
291         .name           = "Toshiba 3.5 inch LCD",
292 #elif defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
293         .name           = "Okaya 3.5 inch LCD",
294 #else
295         .name           = "Unknown Display",
296 #endif
297         .check          = clcdfb_check,
298         .decode         = clcdfb_decode,
299         .disable        = clcd_disable,
300         .enable         = clcd_enable,
301         .setup          = lpc32xx_clcd_setup,
302         .mmap           = lpc32xx_clcd_mmap,
303         .remove         = lpc32xx_clcd_remove,
304 };
305
306 struct amba_device lpc32xx_clcd_device = {
307         .dev                            = {
308                 .coherent_dma_mask      = ~0,
309                 .init_name              = "dev:clcd",
310                 .platform_data          = &lpc32xx_clcd_data,
311         },
312         .res                            = {
313                 .start                  = LPC32XX_LCD_BASE,
314                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
315                 .flags                  = IORESOURCE_MEM,
316         },
317         .dma_mask                       = ~0,
318         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
319 };
320 #endif
321
322 /* AMBA based devices list */
323 static struct amba_device *amba_devs[] __initdata = {
324         &lpc32xx_ssp0_device,
325 #if defined (CONFIG_FB_ARMCLCD)
326         &lpc32xx_clcd_device,
327 #endif
328 #if defined(CONFIG_MMC_ARMMMCI)
329         &lpc32xx_mmc_device,
330 #endif
331 };
332
333 /*
334  * Register AMBA BUS Devices.
335  * Call AMBA device restration after SPI driver probe(),
336  * as LCD controller uses SPI driver for initialization
337  */
338 static int __init fdi3250_amba_devices_register(void)
339 {
340         u32 i = 0;
341
342         /* Add AMBA devices */
343         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
344                 struct amba_device *d = amba_devs[i];
345                 amba_device_register(d, &iomem_resource);
346         }
347
348         return 0;
349 }
350 device_initcall_sync(fdi3250_amba_devices_register);
351
352 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
353 /*
354  *  * Board specific NAND setup data
355  *   */
356 static int nandwp_enable(int enable)
357 {
358         if (enable != 0)
359                 gpio_set_value(NAND_WP_GPIO,0);
360         else
361                 gpio_set_value(NAND_WP_GPIO,1);
362
363         return 1;
364 }
365 #define BLK_SIZE (2048 * 64)
366 static struct mtd_partition fdi3250_nand_partition[] = {
367         {
368                 .name   = "fdi3250-boot",
369                 .offset = 0,
370                 .size   = (BLK_SIZE * 4)
371         },
372         {
373                 .name   = "fdi3250-uboot",
374                 .offset = MTDPART_OFS_APPEND,
375                 .size   = (BLK_SIZE * 6)
376         },
377         {
378                 .name   = "fdi3250-kernel",
379                 .offset = MTDPART_OFS_APPEND,
380                 .size   = (BLK_SIZE * 32)
381         },
382         {
383                 .name   = "fdi3250-jffs2",
384                 .offset = MTDPART_OFS_APPEND,
385                 .size   = MTDPART_SIZ_FULL
386         },
387 };
388 static struct mtd_partition * fdi3250_nand_partitions(int size, int *num_partitions)
389 {
390         *num_partitions = ARRAY_SIZE(fdi3250_nand_partition);
391         return fdi3250_nand_partition;
392 }
393 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
394 {
395         .wdr_clks               = 14,
396         .wwidth                 = 260000000,
397         .whold                  = 104000000,
398         .wsetup                 = 200000000,
399         .rdr_clks               = 14,
400         .rwidth                 = 34666666,
401         .rhold                  = 104000000,
402         .rsetup                 = 200000000,
403         .use_bbt                = true,
404         .polled_completion      = false,
405         .enable_write_prot      = nandwp_enable,
406         .partition_info         = fdi3250_nand_partitions,
407 };
408
409 /*
410  *  * SLC NAND resources
411  *   */
412 static struct resource slc_nand_resources[] = {
413         [0] = {
414                 .start  = LPC32XX_SLC_BASE,
415                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
416                 .flags  = IORESOURCE_MEM,
417         },
418
419         [1] = {
420                 .start  = IRQ_LPC32XX_FLASH,
421                 .end    = IRQ_LPC32XX_FLASH,
422                 .flags  = IORESOURCE_IRQ,
423         },
424
425 };
426
427 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
428 static struct platform_device lpc32xx_slc_nand_device = {
429         .name           = "lpc32xx-nand",
430         .id             = 0,
431         .dev            = {
432                                 .platform_data  = &lpc32xx_nandcfg,
433                                 .dma_mask    = &lpc32xx_slc_dma_mask,
434                                 .coherent_dma_mask = ~0UL,
435
436         },
437         .num_resources  = ARRAY_SIZE(slc_nand_resources),
438         .resource       = slc_nand_resources,
439 };
440 #endif
441
442 /*
443  * Network Support
444  */
445 static struct lpc_net_cfg lpc32xx_netdata =
446 {
447         .phy_irq        = -1,
448         .phy_mask       = 0xFFFFFFF0,
449 };
450
451 static struct resource net_resources[] = {
452         [0] = {
453                 .start  = LPC32XX_ETHERNET_BASE,
454                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
455                 .flags  = IORESOURCE_MEM,
456         },
457
458         [1] = {
459                 .start  = IRQ_LPC32XX_ETHERNET,
460                 .end    = IRQ_LPC32XX_ETHERNET,
461                 .flags  = IORESOURCE_IRQ,
462         },
463
464 };
465
466 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
467 static struct platform_device lpc32xx_net_device = {
468         .name           = "lpc-net",
469         .id             = 0,
470         .dev            = {
471                 .dma_mask = &lpc32xx_mac_dma_mask,
472                 .coherent_dma_mask = 0xffffffffUL,
473                 .platform_data  = &lpc32xx_netdata,
474         },
475         .num_resources  = ARRAY_SIZE(net_resources),
476         .resource       = net_resources,
477 };
478
479 static struct platform_device* fdi3250_devs[] __initdata = {
480         &lpc32xx_i2c0_device,
481         &lpc32xx_i2c1_device,
482         &lpc32xx_i2c2_device,
483         &lpc32xx_watchdog_device,
484         &lpc32xx_gpio_led_device,
485         &lpc32xx_rtc_device,
486         &lpc32xx_tsc_device,
487         &lpc32xx_net_device,
488 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
489         &lpc32xx_slc_nand_device,
490 #endif
491 #if defined(CONFIG_USB_OHCI_HCD)
492         &lpc32xx_ohci_device,
493 #endif
494 #if defined(CONFIG_USB_GADGET_LPC32XX)
495         &lpc32xx_usbd_device,
496 #endif
497 };
498
499 /*
500  * Board specific functions
501  */
502 void __init fdi3250_board_init(void)
503 {
504         u32 tmp;
505
506         /* Intiliase GPIO */
507         lpc32xx_gpio_init();
508
509         /* Set SPI CS GPIO to output */
510         gpio_request(SPI_CS_GPIO, "spi0 cs");
511         gpio_direction_output(SPI_CS_GPIO, 1);
512
513         gpio_request(NAND_WP_GPIO, "NAND WP GPIO");
514         gpio_direction_input(NAND_WP_GPIO);
515
516         /* Setup network interface for RMII mode */
517         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
518         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
519         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
520         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
521
522         /* Setup SLC NAND controller */
523         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
524                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
525
526         /* Setup LCD muxing to RGB565 */
527         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
528                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
529                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
530         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
531         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
532
533         /* Set up I2C pull levels */
534         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
535         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
536                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
537         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
538
539         /* Initalise Serial device */
540         lpc32xx_serial_init();
541
542         /*
543          * AMBA peripheral clocks need to be enabled prior to AMBA device
544          * detection or a data fault will occur, so enable the clocks
545          * here. However, we don't want to enable them if the peripheral
546          * isn't included in the image
547          */
548         /* Initialise SSP clock */
549         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
550         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
551                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
552
553         /* Initialise LCD clock */
554         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
555         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
556                         LPC32XX_CLKPWR_LCDCLK_CTRL);
557
558         /* Enable SD card clock so AMBA driver will work correctly. The
559            AMBA driver needs the clock before the SD card controller
560            driver initializes it. The clock will turn off once the driver
561            has been initialized. */
562         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
563         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
564                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
565         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
566
567         /* Disable UART5->USB transparent mode or USB won't work */
568         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
569         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
570         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
571
572         /* Add platform devcies */
573         platform_add_devices(fdi3250_devs, ARRAY_SIZE(fdi3250_devs));
574 }
575
576 static int __init lpc32xx_display_uid(void)
577 {
578         u32 uid[4];
579
580         lpc32xx_get_uid(uid);
581
582         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
583                         uid[3], uid[2], uid[1], uid[0]);
584
585         return 1;
586 }
587 arch_initcall(lpc32xx_display_uid);
588
589 MACHINE_START (FDI3250, "Future Designs board with the LPC3250 Microcontroller")
590         .phys_io        = LPC32XX_UART5_BASE,
591         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_HS_UART1_BASE))>>18) & 0xfffc,
592         .boot_params    = 0x80000100,
593         .map_io         = lpc32xx_map_io,
594         .init_irq       = lpc32xx_init_irq,
595         .timer          = &lpc32xx_timer,
596         .init_machine   = fdi3250_board_init,
597         MACHINE_END
598
599 /* For backwards compatibility with older bootloaders only */
600 MACHINE_START (LPC3XXX, "Future Designs board with the LPC3250 Microcontroller")
601         .phys_io        = LPC32XX_UART5_BASE,
602         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_HS_UART1_BASE))>>18) & 0xfffc,
603         .boot_params    = 0x80000100,
604         .map_io         = lpc32xx_map_io,
605         .init_irq       = lpc32xx_init_irq,
606         .timer          = &lpc32xx_timer,
607         .init_machine   = fdi3250_board_init,
608         MACHINE_END