mtd: lpc32xx_nand: NAND driver changes
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / fdi3250.c
1 /*
2  * arch/arm/mach-lpc32xx/fdi3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/gpio.h>
29 #include <linux/input.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl022.h>
33 #include <linux/amba/mmci.h>
34
35 #include <asm/setup.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38
39 #include <mach/hardware.h>
40 #include <mach/platform.h>
41 #include <mach/board.h>
42 #include "common.h"
43
44 /*
45  * Mapped GPIOLIB GPIOs
46  */
47 #define LED_GPIO                LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 3)
48 #define SPI_CS_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
49 #define NAND_WP_GPIO            LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
50
51 /*
52  * Tick LED
53  */
54 static struct gpio_led phy_leds[] = {
55         {
56                 .name                   = "led0",
57                 .gpio                   = LED_GPIO,
58                 .active_low             = 1,
59                 .default_trigger        = "heartbeat",
60         },
61 };
62
63 static struct gpio_led_platform_data led_data = {
64         .leds = phy_leds,
65         .num_leds = ARRAY_SIZE(phy_leds),
66 };
67
68 static struct platform_device lpc32xx_gpio_led_device = {
69         .name                   = "leds-gpio",
70         .id                     = -1,
71         .dev.platform_data      = &led_data,
72 };
73
74 /*
75  * AMBA SSP (SPI)
76  */
77 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
78         .bus_id                 = 0,
79         .num_chipselect         = 2,
80         .enable_dma             = 0,
81 };
82
83 static struct amba_device lpc32xx_ssp0_device = {
84         .dev    = {
85                 .coherent_dma_mask      = ~0,
86                 .init_name              = "dev:ssp0",
87                 .platform_data          = &lpc32xx_ssp0_data,
88         },
89         .res                            = {
90                 .start                  = LPC32XX_SSP0_BASE,
91                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
92                 .flags                  = IORESOURCE_MEM,
93         },
94         .dma_mask                       = ~0,
95         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
96 };
97
98 /* SPIDEV chip select function */
99 static void fdi3250_spi_cs_set(u32 control)
100 {
101         gpio_set_value(SPI_CS_GPIO, (int) control);
102 }
103
104 /* SPIDEV parameters */
105 static struct pl022_config_chip spi0_chip_info = {
106         .lbm                    = LOOPBACK_DISABLED,
107         .com_mode               = INTERRUPT_TRANSFER,
108         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
109         .hierarchy              = SSP_MASTER,
110         .slave_tx_disable       = 0,
111         .endian_tx              = SSP_TX_LSB,
112         .endian_rx              = SSP_RX_LSB,
113         .data_size              = SSP_DATA_BITS_8,
114         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
115         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
116         .clk_phase              = SSP_CLK_FIRST_EDGE,
117         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
118         .ctrl_len               = SSP_BITS_8,
119         .wait_state             = SSP_MWIRE_WAIT_ZERO,
120         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
121         .cs_control             = fdi3250_spi_cs_set,
122 };
123
124 /* SPI devices registration */
125 static int __init fdi3250_spi_devices_register(void)
126 {
127         static struct spi_board_info info[] = {
128                 {
129                         .modalias = "spidev",
130                         .max_speed_hz = 2500000,
131                         .bus_num = 0,
132                         .chip_select = 0,
133                         .controller_data = &spi0_chip_info,
134                 },
135         };
136
137         return spi_register_board_info(info, ARRAY_SIZE(info));
138 }
139 arch_initcall(fdi3250_spi_devices_register);
140
141 #if defined (CONFIG_FB_ARMCLCD)
142 /*
143  * Board specific LCD setup and functions
144  */
145 #if defined (CONFIG_SOM9DIMM3250_LCD_PANEL)
146 /*
147  * Support for QVGA portrait panel
148  */
149 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
150 static struct clcd_panel conn_lcd_panel = {
151         .mode           = {
152                 .name           = "QVGA portrait",
153                 .refresh        = 30,
154                 .xres           = 320,
155                 .yres           = 240,
156                 .pixclock       = 158730,
157                 .left_margin    = 11,
158                 .right_margin   = 3,
159                 .upper_margin   = 7,
160                 .lower_margin   = 7,
161                 .hsync_len      = 69,
162                 .vsync_len      = 45,
163                 .sync           = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
164                 .vmode          = FB_VMODE_NONINTERLACED,
165         },
166         .width          = -1,
167         .height         = -1,
168         .tim2           = 0,
169         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
170                                 CNTL_LCDBPP16_565),
171         .bpp            = 16,
172 };
173 #define PANEL_SIZE (3 * SZ_64K)
174 #endif
175 #if defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
176 static struct clcd_panel conn_lcd_panel = {
177         .mode           = {
178                 .name           = "VGA portrait",
179                 .refresh        = 30,
180                 .xres           = 640,
181                 .yres           = 480,
182                 .pixclock       = 41666,
183                 .left_margin    = 10,
184                 .right_margin   = 120,
185                 .upper_margin   = 7,
186                 .lower_margin   = 35,
187                 .hsync_len      = 30,
188                 .vsync_len      = 3,
189                 .sync           = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
190                 .vmode          = FB_VMODE_NONINTERLACED,
191         },
192         .width          = -1,
193         .height         = -1,
194         .tim2           = 0,
195         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
196                                 CNTL_LCDBPP16_565),
197         .bpp            = 16,
198 };
199 #define PANEL_SIZE (10 * SZ_64K)
200 #endif
201
202 #endif // CONFIG_SOM9DIMM3250_LCD_PANEL
203
204 #if defined (CONFIG_MMC_ARMMMCI)
205 static u32 mmc_translate_vdd(struct device *dev, unsigned int vdd)
206 {
207         return 0;
208 }
209
210 unsigned int fdi_mmc_status_always_on(struct device *dev)
211 {
212         return 0;
213 }
214 /*
215  * Board specific MMC driver data
216  */
217 struct mmci_platform_data lpc32xx_plat_data = {
218         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
219         .translate_vdd  = mmc_translate_vdd,
220         .capabilities   = MMC_CAP_4_BIT_DATA,
221         .gpio_wp        = ARCH_NR_GPIOS + 1,
222         .gpio_cd        = ARCH_NR_GPIOS + 1,
223         .status         = fdi_mmc_status_always_on,
224 };
225
226 /*
227  * SD card controller resources
228  */
229 struct amba_device lpc32xx_mmc_device = {
230         .dev = {
231                 .coherent_dma_mask      = ~0,
232                 .init_name                 = "dev:mmc0",
233                 .platform_data          = &lpc32xx_plat_data,
234         },
235         .res = {
236                 .start                  = LPC32XX_SD_BASE,
237                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
238                 .flags                  = IORESOURCE_MEM,
239         },
240         .dma_mask                       = ~0,
241         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
242 };
243 #endif
244
245 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
246 {
247         dma_addr_t dma;
248
249         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
250                         PANEL_SIZE, &dma, GFP_KERNEL);
251         if (!fb->fb.screen_base) {
252                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
253                 return -ENOMEM;
254         }
255
256         fb->fb.fix.smem_start = dma;
257         fb->fb.fix.smem_len = PANEL_SIZE;
258         fb->panel = &conn_lcd_panel;
259
260         return 0;
261 }
262
263 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
264 {
265         return dma_mmap_writecombine(&fb->dev->dev, vma,
266                                      fb->fb.screen_base,
267                                      fb->fb.fix.smem_start,
268                                      fb->fb.fix.smem_len);
269 }
270
271 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
272 {
273         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
274                               fb->fb.screen_base, fb->fb.fix.smem_start);
275 }
276
277 void clcd_disable(struct clcd_fb *fb)
278 {
279 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
280         __raw_writel(0x40000000, io_p2v(LPC32XX_PWM1_BASE));
281 #elif defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
282         __raw_writel(0x00000000, io_p2v(LPC32XX_PWM1_BASE));
283 #endif
284 }
285
286 void clcd_enable(struct clcd_fb *fb)
287 {
288 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
289         __raw_writel(0x00000000, io_p2v(LPC32XX_PWM1_BASE));
290 #elif defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
291         __raw_writel(0x40000000, io_p2v(LPC32XX_PWM1_BASE));
292 #endif
293 }
294
295 struct clcd_board lpc32xx_clcd_data = {
296 #if defined (CONFIG_SOM9DIMM3250_LCD_TOSHIBA_QVGA_35)
297         .name           = "Toshiba 3.5 inch LCD",
298 #elif defined (CONFIG_SOM9DIMM3250_LCD_OKAYA_VGA_35)
299         .name           = "Okaya 3.5 inch LCD",
300 #else
301         .name           = "Unknown Display",
302 #endif
303         .check          = clcdfb_check,
304         .decode         = clcdfb_decode,
305         .disable        = clcd_disable,
306         .enable         = clcd_enable,
307         .setup          = lpc32xx_clcd_setup,
308         .mmap           = lpc32xx_clcd_mmap,
309         .remove         = lpc32xx_clcd_remove,
310 };
311
312 struct amba_device lpc32xx_clcd_device = {
313         .dev                            = {
314                 .coherent_dma_mask      = ~0,
315                 .init_name              = "dev:clcd",
316                 .platform_data          = &lpc32xx_clcd_data,
317         },
318         .res                            = {
319                 .start                  = LPC32XX_LCD_BASE,
320                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
321                 .flags                  = IORESOURCE_MEM,
322         },
323         .dma_mask                       = ~0,
324         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
325 };
326 #endif
327
328 /* AMBA based devices list */
329 static struct amba_device *amba_devs[] __initdata = {
330         &lpc32xx_ssp0_device,
331 #if defined (CONFIG_FB_ARMCLCD)
332         &lpc32xx_clcd_device,
333 #endif
334 #if defined(CONFIG_MMC_ARMMMCI)
335         &lpc32xx_mmc_device,
336 #endif
337 };
338
339 /*
340  * Register AMBA BUS Devices.
341  * Call AMBA device restration after SPI driver probe(),
342  * as LCD controller uses SPI driver for initialization
343  */
344 static int __init fdi3250_amba_devices_register(void)
345 {
346         u32 i = 0;
347
348         /* Add AMBA devices */
349         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
350                 struct amba_device *d = amba_devs[i];
351                 amba_device_register(d, &iomem_resource);
352         }
353
354         return 0;
355 }
356 device_initcall_sync(fdi3250_amba_devices_register);
357
358 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
359 /*
360  *  * Board specific NAND setup data
361  *   */
362 static int nandwp_enable(int enable)
363 {
364         if (enable != 0)
365                 gpio_set_value(NAND_WP_GPIO,0);
366         else
367                 gpio_set_value(NAND_WP_GPIO,1);
368
369         return 1;
370 }
371 #define BLK_SIZE (2048 * 64)
372 static struct mtd_partition fdi3250_nand_partition[] = {
373         {
374                 .name   = "fdi3250-boot",
375                 .offset = 0,
376                 .size   = (BLK_SIZE * 4)
377         },
378         {
379                 .name   = "fdi3250-uboot",
380                 .offset = MTDPART_OFS_APPEND,
381                 .size   = (BLK_SIZE * 6)
382         },
383         {
384                 .name   = "fdi3250-kernel",
385                 .offset = MTDPART_OFS_APPEND,
386                 .size   = (BLK_SIZE * 32)
387         },
388         {
389                 .name   = "fdi3250-jffs2",
390                 .offset = MTDPART_OFS_APPEND,
391                 .size   = MTDPART_SIZ_FULL
392         },
393 };
394 static struct mtd_partition * fdi3250_nand_partitions(int size, int *num_partitions)
395 {
396         *num_partitions = ARRAY_SIZE(fdi3250_nand_partition);
397         return fdi3250_nand_partition;
398 }
399 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
400 {
401         .wdr_clks               = 14,
402         .wwidth                 = 260000000,
403         .whold                  = 104000000,
404         .wsetup                 = 200000000,
405         .rdr_clks               = 14,
406         .rwidth                 = 34666666,
407         .rhold                  = 104000000,
408         .rsetup                 = 200000000,
409         .use_bbt                = true,
410         .polled_completion      = false,
411         .enable_write_prot      = nandwp_enable,
412         .partition_info         = fdi3250_nand_partitions,
413 };
414
415 /*
416  *  * SLC NAND resources
417  *   */
418 static struct resource slc_nand_resources[] = {
419         [0] = {
420                 .start  = LPC32XX_SLC_BASE,
421                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
422                 .flags  = IORESOURCE_MEM,
423         },
424
425         [1] = {
426                 .start  = IRQ_LPC32XX_FLASH,
427                 .end    = IRQ_LPC32XX_FLASH,
428                 .flags  = IORESOURCE_IRQ,
429         },
430
431 };
432
433 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
434 static struct platform_device lpc32xx_slc_nand_device = {
435         .name           = "lpc32xx-nand",
436         .id             = 0,
437         .dev            = {
438                                 .platform_data  = &lpc32xx_nandcfg,
439                                 .dma_mask    = &lpc32xx_slc_dma_mask,
440                                 .coherent_dma_mask = ~0UL,
441
442         },
443         .num_resources  = ARRAY_SIZE(slc_nand_resources),
444         .resource       = slc_nand_resources,
445 };
446 #endif
447
448 /*
449  * Network Support
450  */
451 static struct lpc_net_cfg lpc32xx_netdata =
452 {
453         .phy_irq        = -1,
454         .phy_mask       = 0xFFFFFFF0,
455 };
456
457 static struct resource net_resources[] = {
458         [0] = {
459                 .start  = LPC32XX_ETHERNET_BASE,
460                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
461                 .flags  = IORESOURCE_MEM,
462         },
463
464         [1] = {
465                 .start  = IRQ_LPC32XX_ETHERNET,
466                 .end    = IRQ_LPC32XX_ETHERNET,
467                 .flags  = IORESOURCE_IRQ,
468         },
469
470 };
471
472 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
473 static struct platform_device lpc32xx_net_device = {
474         .name           = "lpc-net",
475         .id             = 0,
476         .dev            = {
477                 .dma_mask = &lpc32xx_mac_dma_mask,
478                 .coherent_dma_mask = 0xffffffffUL,
479                 .platform_data  = &lpc32xx_netdata,
480         },
481         .num_resources  = ARRAY_SIZE(net_resources),
482         .resource       = net_resources,
483 };
484
485 static struct platform_device* fdi3250_devs[] __initdata = {
486         &lpc32xx_i2c0_device,
487         &lpc32xx_i2c1_device,
488         &lpc32xx_i2c2_device,
489         &lpc32xx_watchdog_device,
490         &lpc32xx_gpio_led_device,
491         &lpc32xx_rtc_device,
492         &lpc32xx_tsc_device,
493         &lpc32xx_net_device,
494 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
495         &lpc32xx_slc_nand_device,
496 #endif
497 #if defined(CONFIG_USB_OHCI_HCD)
498         &lpc32xx_ohci_device,
499 #endif
500 #if defined(CONFIG_USB_GADGET_LPC32XX)
501         &lpc32xx_usbd_device,
502 #endif
503 };
504
505 /*
506  * Board specific functions
507  */
508 void __init fdi3250_board_init(void)
509 {
510         u32 tmp;
511
512         /* Intiliase GPIO */
513         lpc32xx_gpio_init();
514
515         /* Set SPI CS GPIO to output */
516         gpio_request(SPI_CS_GPIO, "spi0 cs");
517         gpio_direction_output(SPI_CS_GPIO, 1);
518
519         gpio_request(NAND_WP_GPIO, "NAND WP GPIO");
520         gpio_direction_input(NAND_WP_GPIO);
521
522         /* Setup network interface for RMII mode */
523         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
524         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
525         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
526         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
527
528         /* Setup SLC NAND controller */
529         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
530                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
531
532         /* Setup LCD muxing to RGB565 */
533         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
534                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
535                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
536         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
537         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
538
539         /* Set up I2C pull levels */
540         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
541         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
542                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
543         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
544
545         /* Initalise Serial device */
546         lpc32xx_serial_init();
547
548         /*
549          * AMBA peripheral clocks need to be enabled prior to AMBA device
550          * detection or a data fault will occur, so enable the clocks
551          * here. However, we don't want to enable them if the peripheral
552          * isn't included in the image
553          */
554         /* Initialise SSP clock */
555         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
556         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
557                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
558
559         /* Initialise LCD clock */
560         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
561         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
562                         LPC32XX_CLKPWR_LCDCLK_CTRL);
563
564         /* Enable SD card clock so AMBA driver will work correctly. The
565            AMBA driver needs the clock before the SD card controller
566            driver initializes it. The clock will turn off once the driver
567            has been initialized. */
568         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
569         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
570                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
571         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
572
573         /* Disable UART5->USB transparent mode or USB won't work */
574         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
575         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
576         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
577
578         /* Add platform devcies */
579         platform_add_devices(fdi3250_devs, ARRAY_SIZE(fdi3250_devs));
580 }
581
582 static int __init lpc32xx_display_uid(void)
583 {
584         u32 uid[4];
585
586         lpc32xx_get_uid(uid);
587
588         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
589                         uid[3], uid[2], uid[1], uid[0]);
590
591         return 1;
592 }
593 arch_initcall(lpc32xx_display_uid);
594
595 MACHINE_START (FDI3250, "Future Designs board with the LPC3250 Microcontroller")
596         .phys_io        = LPC32XX_UART5_BASE,
597         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_HS_UART1_BASE))>>18) & 0xfffc,
598         .boot_params    = 0x80000100,
599         .map_io         = lpc32xx_map_io,
600         .init_irq       = lpc32xx_init_irq,
601         .timer          = &lpc32xx_timer,
602         .init_machine   = fdi3250_board_init,
603         MACHINE_END
604
605 /* For backwards compatibility with older bootloaders only */
606 MACHINE_START (LPC3XXX, "Future Designs board with the LPC3250 Microcontroller")
607         .phys_io        = LPC32XX_UART5_BASE,
608         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_HS_UART1_BASE))>>18) & 0xfffc,
609         .boot_params    = 0x80000100,
610         .map_io         = lpc32xx_map_io,
611         .init_irq       = lpc32xx_init_irq,
612         .timer          = &lpc32xx_timer,
613         .init_machine   = fdi3250_board_init,
614         MACHINE_END