Update 1 of the 2.6.34 linux kernel release
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / ea3250.c
1 /*
2  * arch/arm/mach-lpc32xx/ea3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/gpio.h>
29 #include <linux/input.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl022.h>
33 #include <linux/amba/mmci.h>
34
35 #include <asm/setup.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38
39 #include <mach/hardware.h>
40 #include <mach/platform.h>
41 #include <mach/board.h>
42 #include "common.h"
43
44 #include <linux/spi/ads7846.h>
45
46 #define I2C_PCA9532_ADDR 0x60
47 #define I2C_24LC256_ADDR 0x50
48
49 /*
50  * Mapped GPIOLIB GPIOs
51  */
52 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
53 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
54 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
55 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
56 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
57 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
58 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
59
60 /*
61  * LCD controller functions
62  */
63 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
64 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
65 #define PANEL_SIZE      (3 * SZ_64K)
66
67 /* SPI LCDC device structure */
68 struct spi_device *ea3250_spi_lcd_dev = NULL;
69
70 /*
71  * Tick LED
72  */
73 static struct gpio_led phy_leds[] = {
74         {
75                 .name                   = "led0",
76                 .gpio                   = LED_GPIO,
77                 .active_low             = 1,
78                 .default_trigger        = "heartbeat",
79         },
80 };
81
82 static struct gpio_led_platform_data led_data = {
83         .leds = phy_leds,
84         .num_leds = ARRAY_SIZE(phy_leds),
85 };
86
87 static struct platform_device lpc32xx_gpio_led_device = {
88         .name                   = "leds-gpio",
89         .id                     = -1,
90         .dev.platform_data      = &led_data,
91 };
92
93 /*
94  * AMBA SSP (SPI)
95  */
96 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
97         .bus_id                 = 0,
98         .num_chipselect         = 2,
99         .enable_dma             = 0,
100 };
101
102 static struct amba_device lpc32xx_ssp0_device = {
103         .dev    = {
104                 .coherent_dma_mask      = ~0,
105                 .init_name              = "dev:ssp0",
106                 .platform_data          = &lpc32xx_ssp0_data,
107         },
108         .res                            = {
109                 .start                  = LPC32XX_SSP0_BASE,
110                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
111                 .flags                  = IORESOURCE_MEM,
112         },
113         .dma_mask                       = ~0,
114         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
115 };
116
117 /*
118  * Touchscreen device
119  */
120 /* Touch screen chip select function */
121 static void ea3250_spi_cs_set(u32 control)
122 {
123         gpio_set_value(SPI0_CS_GPIO, (int) control);
124 }
125
126 /* Touch screen SPI parameters */
127 static struct pl022_config_chip spi0_chip_info = {
128         .lbm                    = LOOPBACK_DISABLED,
129         .com_mode               = INTERRUPT_TRANSFER,
130         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
131         .hierarchy              = SSP_MASTER,
132         .slave_tx_disable       = 0,
133         .endian_tx              = SSP_TX_LSB,
134         .endian_rx              = SSP_RX_LSB,
135         .data_size              = SSP_DATA_BITS_8,
136         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
137         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
138         .clk_phase              = SSP_CLK_FIRST_EDGE,
139         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
140         .ctrl_len               = SSP_BITS_8,
141         .wait_state             = SSP_MWIRE_WAIT_ZERO,
142         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
143         .cs_control             = ea3250_spi_cs_set,
144 };
145
146 /* Touch screen interrupt status function */
147 static int ea3250_ads7846_pendown_state(void)
148 {
149         u32 tmp = gpio_get_value(ADS_TS_GPIO);
150         return (tmp == 0);
151 }
152
153 /* Touch screen platform data */
154 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
155         .debounce_max   = 10,
156         .debounce_tol   = 3,
157         .pressure_max   = 1024,
158         .get_pendown_state = ea3250_ads7846_pendown_state,
159 };
160
161 /*
162  * SPI based LCDC data
163  */
164 /* LCDC chip select function */
165 static void ea3250_spi_lcdc_cs_set(u32 control)
166 {
167         gpio_set_value(LCD_CS_GPIO, (int) control);
168 }
169
170 /* LCDC SPI parameters */
171 static struct pl022_config_chip spi0_chip_info1 = {
172         .lbm                    = LOOPBACK_DISABLED,
173         .com_mode               = INTERRUPT_TRANSFER,
174         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
175         .hierarchy              = SSP_MASTER,
176         .slave_tx_disable       = 0,
177         .endian_tx              = SSP_TX_LSB,
178         .endian_rx              = SSP_RX_LSB,
179         .data_size              = SSP_DATA_BITS_8,
180         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
181         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
182         .clk_phase              = SSP_CLK_FIRST_EDGE,
183         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
184         .ctrl_len               = SSP_BITS_8,
185         .wait_state             = SSP_MWIRE_WAIT_ZERO,
186         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
187         .cs_control             = ea3250_spi_lcdc_cs_set,
188 };
189
190 /* SPI devices registration */
191 static int __init ea3250_spi_devices_register(void)
192 {
193 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
194         static struct spi_board_info info[] = {
195                 {
196                         .modalias = "spidev",
197                         .max_speed_hz = 2500000,
198                         .bus_num = 0,
199                         .chip_select = 0,
200                         .controller_data = &spi0_chip_info,
201                 },
202         };
203 #else
204         struct spi_board_info info[] = {
205                 {
206                         .modalias      = "ads7846",
207                         .max_speed_hz  = 2500000,
208                         .chip_select   = 0,
209                         .irq           = IRQ_LPC32XX_GPIO_00,
210                         .platform_data = &ea_ads7846_platform_data,
211                         .controller_data = &spi0_chip_info,
212                 },
213                 {
214                         .modalias      = "ea3250_lcdc",
215                         .max_speed_hz  = 10000000,
216                         .chip_select   = 1,
217                         .controller_data = &spi0_chip_info1,
218                 },
219         };
220 #endif
221
222         /* Configure ADS TS INT GPIO pin as input */
223         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
224                 return -EIO;
225         if(gpio_direction_input(ADS_TS_GPIO))
226                 return -EIO;
227
228         /* Configure LCDC CS GPIO pin */
229         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
230                 return -EIO;
231         if(gpio_direction_output(LCD_CS_GPIO, 1))
232                 return -EIO;
233
234         return spi_register_board_info(info, ARRAY_SIZE(info));
235 }
236 arch_initcall(ea3250_spi_devices_register);
237
238 #if defined (CONFIG_FB_ARMCLCD)
239 /*
240  * LCDC AMBA Driver Board Functions
241  */
242 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
243 /*
244  * Support for Embedded Artists 3.2 inch QVGA LCD panel
245  */
246 static struct clcd_panel conn_lcd_panel = {
247         .mode           = {
248                 .name           = "QVGA portrait",
249                 .refresh        = 60,
250                 .xres           = 240,
251                 .yres           = 320,
252                 .pixclock       = 121654,
253                 .left_margin    = 28,
254                 .right_margin   = 10,
255                 .upper_margin   = 2,
256                 .lower_margin   = 2,
257                 .hsync_len      = 2,
258                 .vsync_len      = 2,
259                 .sync           = 0,
260                 .vmode          = FB_VMODE_NONINTERLACED,
261         },
262         .width          = -1,
263         .height         = -1,
264         .tim2           = (TIM2_IVS | TIM2_IHS),
265         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
266                                 CNTL_LCDBPP16_565),
267         .bpp            = 16,
268 };
269
270 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
271 /*
272  * Support for Embedded Artists 2.8 inch QVGA OLED panel
273 */
274 static struct clcd_panel conn_lcd_panel = {
275         .mode           = {
276                 .name           = "QVGA portrait",
277                 .refresh        = 60,
278                 .xres           = 240,
279                 .yres           = 320,
280                 .pixclock       = 176366,
281                 .left_margin    = 33,
282                 .right_margin   = 26,
283                 .upper_margin   = 3,
284                 .lower_margin   = 8,
285                 .hsync_len      = 32,
286                 .vsync_len      = 4,
287                 .sync           = 0,
288                 .vmode          = FB_VMODE_NONINTERLACED,
289         },
290         .width          = -1,
291         .height         = -1,
292         .tim2           = (TIM2_IVS | TIM2_IHS),
293         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
294                                 CNTL_LCDBPP16_565),
295         .bpp            = 16,
296 };
297 #endif
298
299 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
300 {
301         dma_addr_t dma;
302
303         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
304                         PANEL_SIZE, &dma, GFP_KERNEL);
305         if (!fb->fb.screen_base) {
306                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
307                 return -ENOMEM;
308         }
309
310         fb->fb.fix.smem_start = dma;
311         fb->fb.fix.smem_len = PANEL_SIZE;
312         fb->panel = &conn_lcd_panel;
313
314         /* Configure LCDC RS GPIO pin */
315         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
316                 return -EIO;
317
318         if(gpio_direction_output(LCD_RS_GPIO, 1))
319                 return -EIO;
320
321         /* Configure LCDC Backlight GPIO pin */
322         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
323                 return -EIO;
324
325 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
326         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
327 #else
328         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
329 #endif
330                 return -EIO;
331         }
332
333         return 0;
334 }
335
336 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
337 {
338         return dma_mmap_writecombine(&fb->dev->dev, vma,
339                                      fb->fb.screen_base,
340                                      fb->fb.fix.smem_start,
341                                      fb->fb.fix.smem_len);
342 }
343
344 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
345 {
346         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
347                               fb->fb.screen_base, fb->fb.fix.smem_start);
348 }
349
350 static void spiSend(u8 *buf, size_t len)
351 {
352         BUG_ON(ea3250_spi_lcd_dev == NULL);
353         spi_write(ea3250_spi_lcd_dev, buf, len);
354 }
355
356 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
357 static void writeToDisp(u16 data)
358 {
359         u8 buf[3];
360
361         /* Initiliase buffer */
362         buf[0] = 0x72;
363         buf[1] = data >> 8;
364         buf[2] = data & 0xff;
365         spiSend(buf, 3);
366 }
367 #endif
368
369 static void writeToReg(u16 addr, u16 data)
370 {
371         u8 buf[3];
372
373 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
374         RESET_RS;
375         buf[0] = 0x00;
376         buf[1] = addr & 0xff;
377         spiSend(buf, 2);
378
379         SET_RS;
380         buf[0] = data >> 8;
381         buf[1] = data & 0xff;
382         spiSend(buf, 2);
383
384         RESET_RS;
385         buf[0] = 0x00;
386         buf[1] = 0x22;
387         spiSend(buf, 2);
388 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
389         buf[0] = 0x70;
390         buf[1] = data >> 8;
391         buf[2] = data & 0xff;
392         spiSend(buf, 3);
393 #endif
394
395 }
396
397 static void clcd_display_init(void)
398 {
399         u32 tmp;
400
401         /* setup MUX register to use SSP0 */
402         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
403         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
404
405 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
406
407         writeToReg (0x00,0x0001);
408         mdelay(20);
409         writeToReg (0x03,0xA2A4);
410         writeToReg (0x0C,0x0004);
411         writeToReg (0x0D,0x0308);
412         writeToReg (0x0E,0x3000);
413         mdelay(50);
414         writeToReg (0x1E,0x00AF);
415         writeToReg (0x01,0x2B3F);
416         writeToReg (0x02,0x0600);
417         writeToReg (0x10,0x0000);
418         writeToReg (0x07,0x0233);
419         writeToReg (0x0B,0x0039);
420         writeToReg (0x0F,0x0000);
421         mdelay(50);
422
423         writeToReg (0x30,0x0707);
424         writeToReg (0x31,0x0204);
425         writeToReg (0x32,0x0204);
426         writeToReg (0x33,0x0502);
427         writeToReg (0x34,0x0507);
428         writeToReg (0x35,0x0204);
429         writeToReg (0x36,0x0204);
430         writeToReg (0x37,0x0502);
431         writeToReg (0x3A,0x0302);
432         writeToReg (0x3B,0x0302);
433
434         writeToReg (0x23,0x0000);
435         writeToReg (0x24,0x0000);
436
437         writeToReg (0x48,0x0000);
438         writeToReg (0x49,0x013F);
439         writeToReg (0x4A,0x0000);
440         writeToReg (0x4B,0x0000);
441
442         writeToReg (0x41,0x0000);
443         writeToReg (0x42,0x0000);
444
445         writeToReg (0x44,0xEF00);
446         writeToReg (0x45,0x0000);
447         writeToReg (0x46,0x013F);
448         mdelay(50);
449
450         writeToReg (0x44,0xEF00);
451         writeToReg (0x45,0x0000);
452         writeToReg (0x4E,0x0000);
453         writeToReg (0x4F,0x0000);
454         writeToReg (0x46,0x013F);
455
456 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
457
458         writeToReg(0,0x02);
459         writeToDisp(0x0192);
460
461         writeToReg(0,0x03);
462         writeToDisp(0x0130);
463
464         /* set standby off */
465         writeToReg(0,0x10);
466         writeToDisp(0x0000);
467
468         mdelay(100);
469
470         /* set display on */
471         writeToReg(0,0x05);
472         writeToDisp(0x0001);
473
474         /* enable image data transfer */
475         writeToReg(0,0x22);
476 #endif
477 }
478
479 void clcd_disable(struct clcd_fb *fb)
480 {
481         /* Disable the backlight */
482 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
483         gpio_set_value(BKL_POW_GPIO, 1);
484 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
485         gpio_set_value(BKL_POW_GPIO, 0);
486 #endif
487 }
488
489 void clcd_enable(struct clcd_fb *fb)
490 {
491         clcd_display_init();
492
493         /* Enable the backlight */
494 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
495         gpio_set_value(BKL_POW_GPIO, 0);
496 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
497         gpio_set_value(BKL_POW_GPIO, 1);
498 #endif
499
500 }
501
502 struct clcd_board lpc32xx_clcd_data = {
503 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
504         .name           = "Embedded Artists 3.2 inch LCD",
505 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
506         .name           = "Embedded Artists 2.8 inch OLED",
507 #else
508         .name           = "Unknown Display",
509 #endif
510         .check          = clcdfb_check,
511         .decode         = clcdfb_decode,
512         .disable        = clcd_disable,
513         .enable         = clcd_enable,
514         .setup          = lpc32xx_clcd_setup,
515         .mmap           = lpc32xx_clcd_mmap,
516         .remove         = lpc32xx_clcd_remove,
517 };
518
519 struct amba_device lpc32xx_clcd_device = {
520         .dev                            = {
521                 .coherent_dma_mask      = ~0,
522                 .init_name              = "dev:clcd",
523                 .platform_data          = &lpc32xx_clcd_data,
524         },
525         .res                            = {
526                 .start                  = LPC32XX_LCD_BASE,
527                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
528                 .flags                  = IORESOURCE_MEM,
529         },
530         .dma_mask                       = ~0,
531         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
532 };
533 #endif
534
535 /*
536  * SPI LCDC Driver Probe function
537  */
538 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
539 {
540         int err;
541
542         spi->mode = SPI_MODE_0;
543         ea3250_spi_lcd_dev = spi;
544
545         /* SPI settings */
546         err = spi_setup(spi);
547         if (err < 0) {
548                 dev_err(&spi->dev, "Err in setting SPI \n");
549                 return err;
550         }
551         return 0;
552 }
553
554 /*
555  *  * SPI LCDC Driver remove function
556  *   * */
557 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
558 {
559         return 0;
560 }
561
562 static struct spi_driver ea3250_spi_lcdc_driver = {
563         .driver = {
564                 .name   = "ea3250_lcdc",
565                 .bus    = &spi_bus_type,
566                 .owner  = THIS_MODULE,
567         },
568         .probe  = ea3250_spi_lcdc_probe,
569         .remove = __devexit_p(ea3250_spi_lcdc_remove),
570 };
571
572 void __init ea3250_spi_lcdc_drv_init(void)
573 {
574         spi_register_driver(&ea3250_spi_lcdc_driver);
575 }
576
577 /* AMBA based devices list */
578 static struct amba_device *amba_devs[] __initdata = {
579         &lpc32xx_ssp0_device,
580 #if defined (CONFIG_FB_ARMCLCD)
581         &lpc32xx_clcd_device,
582 #endif
583 };
584
585 /*
586  * Register AMBA BUS Devices.
587  * Call AMBA device restration after SPI driver probe(),
588  * as LCD controller uses SPI driver for initialization
589  */
590 static int __init ea3250_amba_devices_register(void)
591 {
592         u32 i = 0;
593
594         /* Add AMBA devices */
595         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
596                 struct amba_device *d = amba_devs[i];
597                 amba_device_register(d, &iomem_resource);
598         }
599         
600         return 0;
601 }
602 device_initcall_sync(ea3250_amba_devices_register);
603
604 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
605 /*
606  *  * Board specific NAND setup data
607  *   */
608 static int nandwp_enable(int enable)
609 {
610         if (enable != 0)
611                 gpio_set_value(NAND_WP_GPIO,0);
612         else
613                 gpio_set_value(NAND_WP_GPIO,1);
614
615         return 1;
616 }
617 #define BLK_SIZE (2048 * 64)
618 static struct mtd_partition __initdata ea3250_nand_partition[] = {
619         {
620                 .name   = "ea3250-boot",
621                 .offset = 0,
622                 .size   = (BLK_SIZE * 25)
623         },
624         {
625                 .name   = "ea3250-uboot",
626                 .offset = MTDPART_OFS_APPEND,
627                 .size   = (BLK_SIZE * 100)
628         },
629         {
630                 .name   = "ea3250-ubt-prms",
631                 .offset = MTDPART_OFS_APPEND,
632                 .size   = (BLK_SIZE * 2)
633         },
634         {
635                 .name   = "ea3250-kernel",
636                 .offset = MTDPART_OFS_APPEND,
637                 .size   = (BLK_SIZE * 32)
638         },
639         {
640                 .name   = "ea3250-jffs2",
641                 .offset = MTDPART_OFS_APPEND,
642                 .size   = MTDPART_SIZ_FULL
643         },
644 };
645 static struct mtd_partition * __init ea3250_nand_partitions(int size, int *num_partitions)
646 {
647         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
648         return ea3250_nand_partition;
649 }
650 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
651 {
652         .wdr_clks               = 14,
653         .wwidth                 = 260000000,
654         .whold                  = 104000000,
655         .wsetup                 = 200000000,
656         .rdr_clks               = 14,
657         .rwidth                 = 34666666,
658         .rhold                  = 104000000,
659         .rsetup                 = 200000000,
660         .use16bus               = 0,
661         .enable_write_prot      = nandwp_enable,
662         .partition_info         = ea3250_nand_partitions,
663 };
664
665 /*
666  *  * SLC NAND resources
667  *   */
668 static struct resource slc_nand_resources[] = {
669         [0] = {
670                 .start  = LPC32XX_SLC_BASE,
671                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
672                 .flags  = IORESOURCE_MEM,
673         },
674
675         [1] = {
676                 .start  = IRQ_LPC32XX_FLASH,
677                 .end    = IRQ_LPC32XX_FLASH,
678                 .flags  = IORESOURCE_IRQ,
679         },
680
681 };
682
683 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
684 static struct platform_device lpc32xx_slc_nand_device = {
685         .name           = "lpc32xx-nand",
686         .id             = 0,
687         .dev            = {
688                                 .platform_data  = &lpc32xx_nandcfg,
689                                 .dma_mask    = &lpc32xx_slc_dma_mask,
690                                 .coherent_dma_mask = ~0UL,
691
692         },
693         .num_resources  = ARRAY_SIZE(slc_nand_resources),
694         .resource       = slc_nand_resources,
695 };
696 #endif
697
698 /*
699  * Network Support
700  */
701 static struct lpc_net_cfg lpc32xx_netdata =
702 {
703         .phy_irq        = -1,
704         .phy_mask       = 0xFFFFFFF0,
705 };
706
707 static struct resource net_resources[] = {
708         [0] = {
709                 .start  = LPC32XX_ETHERNET_BASE,
710                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
711                 .flags  = IORESOURCE_MEM,
712         },
713
714         [1] = {
715                 .start  = IRQ_LPC32XX_ETHERNET,
716                 .end    = IRQ_LPC32XX_ETHERNET,
717                 .flags  = IORESOURCE_IRQ,
718         },
719
720 };
721
722 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
723 static struct platform_device lpc32xx_net_device = {
724         .name           = "lpc-net",
725         .id             = 0,
726         .dev            = {
727                 .dma_mask = &lpc32xx_mac_dma_mask,
728                 .coherent_dma_mask = 0xffffffffUL,
729                 .platform_data  = &lpc32xx_netdata,
730         },
731         .num_resources  = ARRAY_SIZE(net_resources),
732         .resource       = net_resources,
733 };
734
735 /*
736  * I2C devices support
737  */
738 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
739         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
740 #if defined (CONFIG_SENSORS_PCA9532)
741                 {
742                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
743
744                 },
745 #endif
746 #if defined (CONFIG_AT24)
747                 {
748                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
749                 },
750 #endif
751         };
752 #endif
753
754 static struct platform_device* ea3250_devs[] __initdata = {
755         &lpc32xx_i2c0_device,
756         &lpc32xx_i2c1_device,
757         &lpc32xx_i2c2_device,
758         &lpc32xx_watchdog_device,
759         &lpc32xx_gpio_led_device,
760         &lpc32xx_rtc_device,
761         &lpc32xx_net_device,
762 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
763         &lpc32xx_slc_nand_device,
764 #endif
765 #if defined(CONFIG_USB_OHCI_HCD)
766         &lpc32xx_ohci_device,
767 #endif
768 #if defined(CONFIG_USB_GADGET_LPC32XX)
769         &lpc32xx_usbd_device,
770 #endif
771 };
772
773 extern void __init ea3250_spi_lcdc_drv_init(void);
774
775 /*
776  * Board specific functions
777  */
778 void __init ea3250_board_init(void)
779 {
780         u32 tmp;
781
782         /* Intiliase GPIO */
783         lpc32xx_gpio_init();
784
785         /* Set SPI CS GPIO to output */
786         gpio_request(SPI0_CS_GPIO, "spi0 cs");
787         gpio_direction_output(SPI0_CS_GPIO, 1);
788
789         /* Setup network interface for RMII mode */
790         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
791         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
792         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
793         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
794
795         /* Setup SLC NAND controller */
796         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
797                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
798
799         /* Setup LCD muxing to RGB565 */
800         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
801                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
802                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
803         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
804         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
805
806         /* Set up I2C pull levels */
807         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
808         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
809                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
810         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
811
812         /* Enable DMA for I2S1 channel */
813         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
814         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
815         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
816
817         /* Initalise Serial device */
818         lpc32xx_serial_init();
819
820         /*
821          * AMBA peripheral clocks need to be enabled prior to AMBA device
822          * detection or a data fault will occur, so enable the clocks
823          * here. However, we don't want to enable them if the peripheral
824          * isn't included in the image
825          */
826         /* Initialise SSP clock */
827         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
828         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
829                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
830
831         /* Initialise LCD clock */
832         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
833         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
834                         LPC32XX_CLKPWR_LCDCLK_CTRL);
835
836         /* Enable SD card clock so AMBA driver will work correctly. The
837            AMBA driver needs the clock before the SD card controller
838            driver initializes it. The clock will turn off once the driver
839            has been initialized. */
840         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
841         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
842                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
843         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
844
845         /* Disable UART5->USB transparent mode or USB won't work */
846         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
847         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
848         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
849
850         /* Add platform devcies */
851         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
852
853         /* Register SPI driver */
854         ea3250_spi_lcdc_drv_init();
855         
856         /* Test clock needed for UDA1380 initial init */
857         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
858                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
859                         LPC32XX_CLKPWR_TEST_CLK_SEL);
860
861 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
862         i2c_register_board_info(0, ea3250_i2c_board_info,
863                         ARRAY_SIZE(ea3250_i2c_board_info));
864 #endif
865 }
866
867 static int __init lpc32xx_display_uid(void)
868 {
869         u32 uid[4];
870
871         lpc32xx_get_uid(uid);
872
873         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
874                         uid[3], uid[2], uid[1], uid[0]);
875
876         return 1;
877 }
878 arch_initcall(lpc32xx_display_uid);
879
880 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
881         /* Maintainer: Embedded Artists */
882         .phys_io        = LPC32XX_UART5_BASE,
883         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
884         .boot_params    = 0x80000100,
885         .map_io         = lpc32xx_map_io,
886         .init_irq       = lpc32xx_init_irq,
887         .timer          = &lpc32xx_timer,
888         .init_machine   = ea3250_board_init,
889         MACHINE_END
890
891 /* For backwards compatibility with older bootloaders only */
892 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
893         /* Maintainer: Embedded Artists */
894         .phys_io        = LPC32XX_UART5_BASE,
895         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
896         .boot_params    = 0x80000100,
897         .map_io         = lpc32xx_map_io,
898         .init_irq       = lpc32xx_init_irq,
899         .timer          = &lpc32xx_timer,
900         .init_machine   = ea3250_board_init,
901         MACHINE_END