ff80325a12bc93d9a395df88243a283d40758545
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / ea3250.c
1 /*
2  * arch/arm/mach-lpc32xx/ea3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/gpio.h>
29 #include <linux/input.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl022.h>
33 #include <linux/amba/mmci.h>
34 #include <mtd/mtd-abi.h>
35
36 #include <asm/setup.h>
37 #include <asm/mach-types.h>
38 #include <asm/mach/arch.h>
39
40 #include <mach/hardware.h>
41 #include <mach/platform.h>
42 #include <mach/board.h>
43 #include "common.h"
44
45 #include <linux/spi/ads7846.h>
46
47 #define I2C_PCA9532_ADDR 0x60
48 #define I2C_24LC256_ADDR 0x50
49
50 /*
51  * Mapped GPIOLIB GPIOs
52  */
53 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
54 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
55 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
56 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
57 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
58 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
59 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
60 #define SSEL0_GPIO5     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
61
62 /*
63  * LCD controller functions
64  */
65 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
66 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
67 #define PANEL_SIZE      (3 * SZ_64K)
68
69 /* SPI LCDC device structure */
70 struct spi_device *ea3250_spi_lcd_dev = NULL;
71
72 /*
73  * Tick LED
74  */
75 static struct gpio_led phy_leds[] = {
76         {
77                 .name                   = "led0",
78                 .gpio                   = LED_GPIO,
79                 .active_low             = 1,
80                 .default_trigger        = "heartbeat",
81         },
82 };
83
84 static struct gpio_led_platform_data led_data = {
85         .leds = phy_leds,
86         .num_leds = ARRAY_SIZE(phy_leds),
87 };
88
89 static struct platform_device lpc32xx_gpio_led_device = {
90         .name                   = "leds-gpio",
91         .id                     = -1,
92         .dev.platform_data      = &led_data,
93 };
94
95 /*
96  * AMBA SSP (SPI)
97  */
98 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
99         .bus_id                 = 0,
100         .num_chipselect         = 2,
101         .enable_dma             = 0,
102 };
103
104 static struct amba_device lpc32xx_ssp0_device = {
105         .dev    = {
106                 .coherent_dma_mask      = ~0,
107                 .init_name              = "dev:ssp0",
108                 .platform_data          = &lpc32xx_ssp0_data,
109         },
110         .res                            = {
111                 .start                  = LPC32XX_SSP0_BASE,
112                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
113                 .flags                  = IORESOURCE_MEM,
114         },
115         .dma_mask                       = ~0,
116         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
117 };
118
119 /*
120  * Touchscreen device
121  */
122 /* Touch screen chip select function */
123 static void ea3250_spi_cs_set(u32 control)
124 {
125         gpio_set_value(SPI0_CS_GPIO, (int) control);
126 }
127
128 /* Touch screen SPI parameters */
129 static struct pl022_config_chip spi0_chip_info = {
130         .lbm                    = LOOPBACK_DISABLED,
131         .com_mode               = INTERRUPT_TRANSFER,
132         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
133         .hierarchy              = SSP_MASTER,
134         .slave_tx_disable       = 0,
135         .endian_tx              = SSP_TX_LSB,
136         .endian_rx              = SSP_RX_LSB,
137         .data_size              = SSP_DATA_BITS_8,
138         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
139         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
140         .clk_phase              = SSP_CLK_FIRST_EDGE,
141         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
142         .ctrl_len               = SSP_BITS_8,
143         .wait_state             = SSP_MWIRE_WAIT_ZERO,
144         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
145         .cs_control             = ea3250_spi_cs_set,
146 };
147
148 /* Touch screen interrupt status function */
149 static int ea3250_ads7846_pendown_state(void)
150 {
151         u32 tmp = gpio_get_value(ADS_TS_GPIO);
152         return (tmp == 0);
153 }
154
155 /* Touch screen platform data */
156 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
157         .debounce_max   = 10,
158         .debounce_tol   = 3,
159         .pressure_max   = 1024,
160         .get_pendown_state = ea3250_ads7846_pendown_state,
161 };
162
163 /*
164  * SPI based LCDC data
165  */
166 /* LCDC chip select function */
167 static void ea3250_spi_lcdc_cs_set(u32 control)
168 {
169         gpio_set_value(LCD_CS_GPIO, (int) control);
170 }
171
172 /* LCDC SPI parameters */
173 static struct pl022_config_chip spi0_chip_info1 = {
174         .lbm                    = LOOPBACK_DISABLED,
175         .com_mode               = INTERRUPT_TRANSFER,
176         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
177         .hierarchy              = SSP_MASTER,
178         .slave_tx_disable       = 0,
179         .endian_tx              = SSP_TX_LSB,
180         .endian_rx              = SSP_RX_LSB,
181         .data_size              = SSP_DATA_BITS_8,
182         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
183         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
184         .clk_phase              = SSP_CLK_FIRST_EDGE,
185         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
186         .ctrl_len               = SSP_BITS_8,
187         .wait_state             = SSP_MWIRE_WAIT_ZERO,
188         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
189         .cs_control             = ea3250_spi_lcdc_cs_set,
190 };
191
192 /* SPI devices registration */
193 static int __init ea3250_spi_devices_register(void)
194 {
195 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
196         static struct spi_board_info info[] = {
197                 {
198                         .modalias = "spidev",
199                         .max_speed_hz = 2500000,
200                         .bus_num = 0,
201                         .chip_select = 0,
202                         .controller_data = &spi0_chip_info,
203                 },
204         };
205 #else
206         struct spi_board_info info[] = {
207                 {
208                         .modalias      = "ads7846",
209                         .max_speed_hz  = 2500000,
210                         .chip_select   = 0,
211                         .irq           = IRQ_LPC32XX_GPIO_00,
212                         .platform_data = &ea_ads7846_platform_data,
213                         .controller_data = &spi0_chip_info,
214                 },
215                 {
216                         .modalias      = "ea3250_lcdc",
217                         .max_speed_hz  = 10000000,
218                         .chip_select   = 1,
219                         .controller_data = &spi0_chip_info1,
220                 },
221         };
222 #endif
223
224         /* Configure ADS TS INT GPIO pin as input */
225         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
226                 return -EIO;
227         if(gpio_direction_input(ADS_TS_GPIO))
228                 return -EIO;
229
230         /* Configure LCDC CS GPIO pin */
231         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
232                 return -EIO;
233         if(gpio_direction_output(LCD_CS_GPIO, 1))
234                 return -EIO;
235
236         return spi_register_board_info(info, ARRAY_SIZE(info));
237 }
238 arch_initcall(ea3250_spi_devices_register);
239
240 #if defined (CONFIG_FB_ARMCLCD)
241 /*
242  * LCDC AMBA Driver Board Functions
243  */
244 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
245 /*
246  * Support for Embedded Artists 3.2 inch QVGA LCD panel
247  */
248 static struct clcd_panel conn_lcd_panel = {
249         .mode           = {
250                 .name           = "QVGA portrait",
251                 .refresh        = 60,
252                 .xres           = 240,
253                 .yres           = 320,
254                 .pixclock       = 121654,
255                 .left_margin    = 28,
256                 .right_margin   = 10,
257                 .upper_margin   = 2,
258                 .lower_margin   = 2,
259                 .hsync_len      = 3,
260                 .vsync_len      = 2,
261                 .sync           = 0,
262                 .vmode          = FB_VMODE_NONINTERLACED,
263         },
264         .width          = -1,
265         .height         = -1,
266         .tim2           = (TIM2_IVS | TIM2_IHS),
267         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
268                                 CNTL_LCDBPP16_565),
269         .bpp            = 16,
270 };
271
272 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
273 /*
274  * Support for Embedded Artists 2.8 inch QVGA OLED panel
275 */
276 static struct clcd_panel conn_lcd_panel = {
277         .mode           = {
278                 .name           = "QVGA portrait",
279                 .refresh        = 60,
280                 .xres           = 240,
281                 .yres           = 320,
282                 .pixclock       = 176366,
283                 .left_margin    = 33,
284                 .right_margin   = 26,
285                 .upper_margin   = 3,
286                 .lower_margin   = 8,
287                 .hsync_len      = 32,
288                 .vsync_len      = 4,
289                 .sync           = 0,
290                 .vmode          = FB_VMODE_NONINTERLACED,
291         },
292         .width          = -1,
293         .height         = -1,
294         .tim2           = (TIM2_IVS | TIM2_IHS),
295         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
296                                 CNTL_LCDBPP16_565),
297         .bpp            = 16,
298 };
299 #endif
300
301 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
302 {
303         dma_addr_t dma;
304
305         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
306                         PANEL_SIZE, &dma, GFP_KERNEL);
307         if (!fb->fb.screen_base) {
308                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
309                 return -ENOMEM;
310         }
311
312         fb->fb.fix.smem_start = dma;
313         fb->fb.fix.smem_len = PANEL_SIZE;
314         fb->panel = &conn_lcd_panel;
315
316         if (gpio_request(SSEL0_GPIO5, "Unused GPIO5 input"))
317                 return -EIO;
318         if(gpio_direction_input(SSEL0_GPIO5))
319                 return -EIO;
320
321         /* Configure LCDC RS GPIO pin */
322         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
323                 return -EIO;
324
325         if(gpio_direction_output(LCD_RS_GPIO, 1))
326                 return -EIO;
327
328         /* Configure LCDC Backlight GPIO pin */
329         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
330                 return -EIO;
331
332 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
333         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
334 #else
335         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
336 #endif
337                 return -EIO;
338         }
339
340         return 0;
341 }
342
343 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
344 {
345         return dma_mmap_writecombine(&fb->dev->dev, vma,
346                                      fb->fb.screen_base,
347                                      fb->fb.fix.smem_start,
348                                      fb->fb.fix.smem_len);
349 }
350
351 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
352 {
353         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
354                               fb->fb.screen_base, fb->fb.fix.smem_start);
355 }
356
357 static void spiSend(u8 *buf, size_t len)
358 {
359         BUG_ON(ea3250_spi_lcd_dev == NULL);
360         spi_write(ea3250_spi_lcd_dev, buf, len);
361 }
362
363 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
364 static void writeToDisp(u16 data)
365 {
366         u8 buf[3];
367
368         /* Initiliase buffer */
369         buf[0] = 0x72;
370         buf[1] = data >> 8;
371         buf[2] = data & 0xff;
372         spiSend(buf, 3);
373 }
374 #endif
375
376 static void writeToReg(u16 addr, u16 data)
377 {
378         u8 buf[3];
379
380 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
381         RESET_RS;
382         buf[0] = 0x00;
383         buf[1] = addr & 0xff;
384         spiSend(buf, 2);
385
386         SET_RS;
387         buf[0] = data >> 8;
388         buf[1] = data & 0xff;
389         spiSend(buf, 2);
390
391         RESET_RS;
392         buf[0] = 0x00;
393         buf[1] = 0x22;
394         spiSend(buf, 2);
395 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
396         buf[0] = 0x70;
397         buf[1] = data >> 8;
398         buf[2] = data & 0xff;
399         spiSend(buf, 3);
400 #endif
401
402 }
403
404 static void clcd_display_init(void)
405 {
406         u32 tmp;
407
408         /* setup MUX register to use SSP0 */
409         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
410         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
411
412 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
413
414         writeToReg (0x00,0x0001);
415         mdelay(20);
416         writeToReg (0x03,0xA2A4);
417         writeToReg (0x0C,0x0004);
418         writeToReg (0x0D,0x0308);
419         writeToReg (0x0E,0x3000);
420         mdelay(50);
421         writeToReg (0x1E,0x00AF);
422         writeToReg (0x01,0x2B3F);
423         writeToReg (0x02,0x0600);
424         writeToReg (0x10,0x0000);
425         writeToReg (0x07,0x0233);
426         writeToReg (0x0B,0x0039);
427         writeToReg (0x0F,0x0000);
428         mdelay(50);
429
430         writeToReg (0x30,0x0707);
431         writeToReg (0x31,0x0204);
432         writeToReg (0x32,0x0204);
433         writeToReg (0x33,0x0502);
434         writeToReg (0x34,0x0507);
435         writeToReg (0x35,0x0204);
436         writeToReg (0x36,0x0204);
437         writeToReg (0x37,0x0502);
438         writeToReg (0x3A,0x0302);
439         writeToReg (0x3B,0x0302);
440
441         writeToReg (0x23,0x0000);
442         writeToReg (0x24,0x0000);
443
444         writeToReg (0x48,0x0000);
445         writeToReg (0x49,0x013F);
446         writeToReg (0x4A,0x0000);
447         writeToReg (0x4B,0x0000);
448
449         writeToReg (0x41,0x0000);
450         writeToReg (0x42,0x0000);
451
452         writeToReg (0x44,0xEF00);
453         writeToReg (0x45,0x0000);
454         writeToReg (0x46,0x013F);
455         mdelay(50);
456
457         writeToReg (0x44,0xEF00);
458         writeToReg (0x45,0x0000);
459         writeToReg (0x4E,0x0000);
460         writeToReg (0x4F,0x0000);
461         writeToReg (0x46,0x013F);
462
463 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
464
465         writeToReg(0,0x02);
466         writeToDisp(0x0192);
467
468         writeToReg(0,0x03);
469         writeToDisp(0x0130);
470
471         /* set standby off */
472         writeToReg(0,0x10);
473         writeToDisp(0x0000);
474
475         mdelay(100);
476
477         /* set display on */
478         writeToReg(0,0x05);
479         writeToDisp(0x0001);
480
481         /* enable image data transfer */
482         writeToReg(0,0x22);
483 #endif
484 }
485
486 void clcd_disable(struct clcd_fb *fb)
487 {
488         /* Disable the backlight */
489 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
490         gpio_set_value(BKL_POW_GPIO, 1);
491 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
492         gpio_set_value(BKL_POW_GPIO, 0);
493 #endif
494 }
495
496 void clcd_enable(struct clcd_fb *fb)
497 {
498         clcd_display_init();
499
500         /* Enable the backlight */
501 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
502         gpio_set_value(BKL_POW_GPIO, 0);
503 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
504         gpio_set_value(BKL_POW_GPIO, 1);
505 #endif
506
507 }
508
509 struct clcd_board lpc32xx_clcd_data = {
510 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
511         .name           = "Embedded Artists 3.2 inch LCD",
512 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
513         .name           = "Embedded Artists 2.8 inch OLED",
514 #else
515         .name           = "Unknown Display",
516 #endif
517         .check          = clcdfb_check,
518         .decode         = clcdfb_decode,
519         .disable        = clcd_disable,
520         .enable         = clcd_enable,
521         .setup          = lpc32xx_clcd_setup,
522         .mmap           = lpc32xx_clcd_mmap,
523         .remove         = lpc32xx_clcd_remove,
524 };
525
526 struct amba_device lpc32xx_clcd_device = {
527         .dev                            = {
528                 .coherent_dma_mask      = ~0,
529                 .init_name              = "dev:clcd",
530                 .platform_data          = &lpc32xx_clcd_data,
531         },
532         .res                            = {
533                 .start                  = LPC32XX_LCD_BASE,
534                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
535                 .flags                  = IORESOURCE_MEM,
536         },
537         .dma_mask                       = ~0,
538         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
539 };
540 #endif
541
542 /*
543  * SPI LCDC Driver Probe function
544  */
545 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
546 {
547         int err;
548
549         spi->mode = SPI_MODE_0;
550         ea3250_spi_lcd_dev = spi;
551
552         /* SPI settings */
553         err = spi_setup(spi);
554         if (err < 0) {
555                 dev_err(&spi->dev, "Err in setting SPI \n");
556                 return err;
557         }
558         return 0;
559 }
560
561 /*
562  *  * SPI LCDC Driver remove function
563  *   * */
564 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
565 {
566         return 0;
567 }
568
569 static struct spi_driver ea3250_spi_lcdc_driver = {
570         .driver = {
571                 .name   = "ea3250_lcdc",
572                 .bus    = &spi_bus_type,
573                 .owner  = THIS_MODULE,
574         },
575         .probe  = ea3250_spi_lcdc_probe,
576         .remove = __devexit_p(ea3250_spi_lcdc_remove),
577 };
578
579 void __init ea3250_spi_lcdc_drv_init(void)
580 {
581         spi_register_driver(&ea3250_spi_lcdc_driver);
582 }
583
584 /* AMBA based devices list */
585 static struct amba_device *amba_devs[] __initdata = {
586         &lpc32xx_ssp0_device,
587 #if defined (CONFIG_FB_ARMCLCD)
588         &lpc32xx_clcd_device,
589 #endif
590 };
591
592 /*
593  * Register AMBA BUS Devices.
594  * Call AMBA device restration after SPI driver probe(),
595  * as LCD controller uses SPI driver for initialization
596  */
597 static int __init ea3250_amba_devices_register(void)
598 {
599         u32 i = 0;
600
601         /* Add AMBA devices */
602         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
603                 struct amba_device *d = amba_devs[i];
604                 amba_device_register(d, &iomem_resource);
605         }
606
607         return 0;
608 }
609 device_initcall_sync(ea3250_amba_devices_register);
610
611 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
612 /*
613  *  * Board specific NAND setup data
614  *   */
615 static int nandwp_enable(int enable)
616 {
617         if (enable != 0)
618                 gpio_set_value(NAND_WP_GPIO,0);
619         else
620                 gpio_set_value(NAND_WP_GPIO,1);
621
622         return 1;
623 }
624 #define BLK_SIZE (2048 * 64)
625 static struct mtd_partition ea3250_nand_partition[] = {
626         {
627                 .name   = "ea3250-boot",
628                 .offset = 0,
629                 .size   = (BLK_SIZE * 4),
630                 .mask_flags   = MTD_WRITEABLE,
631         },
632         {
633                 .name   = "ea3250-uboot",
634                 .offset = MTDPART_OFS_APPEND,
635                 .size   = (BLK_SIZE * 6)
636         },
637         {
638                 .name   = "ea3250-kernel",
639                 .offset = MTDPART_OFS_APPEND,
640                 .size   = (BLK_SIZE * 32)
641         },
642         {
643                 .name   = "ea3250-jffs2",
644                 .offset = MTDPART_OFS_APPEND,
645                 .size   = MTDPART_SIZ_FULL
646         },
647 };
648 static struct mtd_partition * ea3250_nand_partitions(int size, int *num_partitions)
649 {
650         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
651         return ea3250_nand_partition;
652 }
653 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
654 {
655         .wdr_clks               = 14,
656         .wwidth                 = 260000000,
657         .whold                  = 104000000,
658         .wsetup                 = 200000000,
659         .rdr_clks               = 14,
660         .rwidth                 = 34666666,
661         .rhold                  = 104000000,
662         .rsetup                 = 200000000,
663         .use_bbt                = true,
664         .polled_completion      = false,
665         .enable_write_prot      = nandwp_enable,
666         .partition_info         = ea3250_nand_partitions,
667 };
668
669 /*
670  *  * SLC NAND resources
671  *   */
672 static struct resource slc_nand_resources[] = {
673         [0] = {
674                 .start  = LPC32XX_SLC_BASE,
675                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
676                 .flags  = IORESOURCE_MEM,
677         },
678
679         [1] = {
680                 .start  = IRQ_LPC32XX_FLASH,
681                 .end    = IRQ_LPC32XX_FLASH,
682                 .flags  = IORESOURCE_IRQ,
683         },
684
685 };
686
687 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
688 static struct platform_device lpc32xx_slc_nand_device = {
689         .name           = "lpc32xx-nand",
690         .id             = 0,
691         .dev            = {
692                                 .platform_data  = &lpc32xx_nandcfg,
693                                 .dma_mask    = &lpc32xx_slc_dma_mask,
694                                 .coherent_dma_mask = ~0UL,
695
696         },
697         .num_resources  = ARRAY_SIZE(slc_nand_resources),
698         .resource       = slc_nand_resources,
699 };
700 #endif
701
702 /*
703  * Network Support
704  */
705 static struct lpc_net_cfg lpc32xx_netdata =
706 {
707         .phy_irq        = -1,
708         .phy_mask       = 0xFFFFFFF0,
709 };
710
711 static struct resource net_resources[] = {
712         [0] = {
713                 .start  = LPC32XX_ETHERNET_BASE,
714                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
715                 .flags  = IORESOURCE_MEM,
716         },
717
718         [1] = {
719                 .start  = IRQ_LPC32XX_ETHERNET,
720                 .end    = IRQ_LPC32XX_ETHERNET,
721                 .flags  = IORESOURCE_IRQ,
722         },
723
724 };
725
726 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
727 static struct platform_device lpc32xx_net_device = {
728         .name           = "lpc-net",
729         .id             = 0,
730         .dev            = {
731                 .dma_mask = &lpc32xx_mac_dma_mask,
732                 .coherent_dma_mask = 0xffffffffUL,
733                 .platform_data  = &lpc32xx_netdata,
734         },
735         .num_resources  = ARRAY_SIZE(net_resources),
736         .resource       = net_resources,
737 };
738
739 /*
740  * I2C devices support
741  */
742 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
743         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
744 #if defined (CONFIG_SENSORS_PCA9532)
745                 {
746                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
747
748                 },
749 #endif
750 #if defined (CONFIG_AT24)
751                 {
752                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
753                 },
754 #endif
755         };
756 #endif
757
758 static struct platform_device* ea3250_devs[] __initdata = {
759         &lpc32xx_i2c0_device,
760         &lpc32xx_i2c1_device,
761         &lpc32xx_i2c2_device,
762         &lpc32xx_watchdog_device,
763         &lpc32xx_gpio_led_device,
764         &lpc32xx_rtc_device,
765         &lpc32xx_net_device,
766 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
767         &lpc32xx_slc_nand_device,
768 #endif
769 #if defined(CONFIG_USB_OHCI_HCD)
770         &lpc32xx_ohci_device,
771 #endif
772 #if defined(CONFIG_USB_GADGET_LPC32XX)
773         &lpc32xx_usbd_device,
774 #endif
775 };
776
777 extern void __init ea3250_spi_lcdc_drv_init(void);
778
779 /*
780  * Board specific functions
781  */
782 void __init ea3250_board_init(void)
783 {
784         u32 tmp;
785
786         /* Intiliase GPIO */
787         lpc32xx_gpio_init();
788
789         /* Set SPI CS GPIO to output */
790         gpio_request(SPI0_CS_GPIO, "spi0 cs");
791         gpio_direction_output(SPI0_CS_GPIO, 1);
792
793         /* Setup network interface for RMII mode */
794         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
795         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
796         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
797         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
798
799         /* Setup SLC NAND controller */
800         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
801                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
802
803         /* Setup LCD muxing to RGB565 */
804         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
805                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
806                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
807         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
808         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
809
810         /* Set up I2C pull levels */
811         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
812         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
813                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
814         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
815
816         /* Enable DMA for I2S1 channel */
817         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
818         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
819         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
820
821         /* Initalise Serial device */
822         lpc32xx_serial_init();
823
824         /*
825          * AMBA peripheral clocks need to be enabled prior to AMBA device
826          * detection or a data fault will occur, so enable the clocks
827          * here. However, we don't want to enable them if the peripheral
828          * isn't included in the image
829          */
830         /* Initialise SSP clock */
831         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
832         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
833                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
834
835         /* Initialise LCD clock */
836         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
837         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
838                         LPC32XX_CLKPWR_LCDCLK_CTRL);
839
840         /* Enable SD card clock so AMBA driver will work correctly. The
841            AMBA driver needs the clock before the SD card controller
842            driver initializes it. The clock will turn off once the driver
843            has been initialized. */
844         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
845         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
846                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
847         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
848
849         /* Disable UART5->USB transparent mode or USB won't work */
850         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
851         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
852         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
853
854         /* Add platform devcies */
855         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
856
857         /* Register SPI driver */
858         ea3250_spi_lcdc_drv_init();
859
860         /* Test clock needed for UDA1380 initial init */
861         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
862                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
863                         LPC32XX_CLKPWR_TEST_CLK_SEL);
864
865 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
866         i2c_register_board_info(0, ea3250_i2c_board_info,
867                         ARRAY_SIZE(ea3250_i2c_board_info));
868 #endif
869 }
870
871 static int __init lpc32xx_display_uid(void)
872 {
873         u32 uid[4];
874
875         lpc32xx_get_uid(uid);
876
877         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
878                         uid[3], uid[2], uid[1], uid[0]);
879
880         return 1;
881 }
882 arch_initcall(lpc32xx_display_uid);
883
884 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
885         /* Maintainer: Embedded Artists */
886         .phys_io        = LPC32XX_UART5_BASE,
887         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
888         .boot_params    = 0x80000100,
889         .map_io         = lpc32xx_map_io,
890         .init_irq       = lpc32xx_init_irq,
891         .timer          = &lpc32xx_timer,
892         .init_machine   = ea3250_board_init,
893         MACHINE_END
894
895 /* For backwards compatibility with older bootloaders only */
896 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
897         /* Maintainer: Embedded Artists */
898         .phys_io        = LPC32XX_UART5_BASE,
899         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
900         .boot_params    = 0x80000100,
901         .map_io         = lpc32xx_map_io,
902         .init_irq       = lpc32xx_init_irq,
903         .timer          = &lpc32xx_timer,
904         .init_machine   = ea3250_board_init,
905         MACHINE_END