arch/arm/mach-lpc32xx/ea3250.c

   1 /*
   2  * arch/arm/mach-lpc32xx/ea3250.c
   3  *
   4  * Copyright (C) 2010 NXP Semiconductors
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/spi/eeprom.h>
  27 #include <linux/leds.h>
  28 #include <linux/gpio.h>
  29 #include <linux/input.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/amba/clcd.h>
  32 #include <linux/amba/pl022.h>
  33 #include <linux/amba/mmci.h>
  34
  35 #include <asm/setup.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/arch.h>
  38
  39 #include <mach/hardware.h>
  40 #include <mach/platform.h>
  41 #include <mach/board.h>
  42 #include "common.h"
  43
  44 #include <linux/spi/ads7846.h>
  45
  46 #define I2C_PCA9532_ADDR 0x60
  47 #define I2C_24LC256_ADDR 0x50
  48
  49 /*
  50  * Mapped GPIOLIB GPIOs
  51  */
  52 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
  53 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
  54 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
  55 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
  56 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
  57 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
  58 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
  59
  60 /*
  61  * LCD controller functions
  62  */
  63 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
  64 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
  65 #define PANEL_SIZE      (3 * SZ_64K)
  66
  67 /* SPI LCDC device structure */
  68 struct spi_device *ea3250_spi_lcd_dev = NULL;
  69
  70 /*
  71  * Tick LED
  72  */
  73 static struct gpio_led phy_leds[] = {
  74         {
  75                 .name                   = "led0",
  76                 .gpio                   = LED_GPIO,
  77                 .active_low             = 1,
  78                 .default_trigger        = "heartbeat",
  79         },
  80 };
  81
  82 static struct gpio_led_platform_data led_data = {
  83         .leds = phy_leds,
  84         .num_leds = ARRAY_SIZE(phy_leds),
  85 };
  86
  87 static struct platform_device lpc32xx_gpio_led_device = {
  88         .name                   = "leds-gpio",
  89         .id                     = -1,
  90         .dev.platform_data      = &led_data,
  91 };
  92
  93 /*
  94  * AMBA SSP (SPI)
  95  */
  96 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
  97         .bus_id                 = 0,
  98         .num_chipselect         = 2,
  99         .enable_dma             = 0,
 100 };
 101
 102 static struct amba_device lpc32xx_ssp0_device = {
 103         .dev    = {
 104                 .coherent_dma_mask      = ~0,
 105                 .init_name              = "dev:ssp0",
 106                 .platform_data          = &lpc32xx_ssp0_data,
 107         },
 108         .res                            = {
 109                 .start                  = LPC32XX_SSP0_BASE,
 110                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
 111                 .flags                  = IORESOURCE_MEM,
 112         },
 113         .dma_mask                       = ~0,
 114         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
 115 };
 116
 117 /*
 118  * Touchscreen device
 119  */
 120 /* Touch screen chip select function */
 121 static void ea3250_spi_cs_set(u32 control)
 122 {
 123         gpio_set_value(SPI0_CS_GPIO, (int) control);
 124 }
 125
 126 /* Touch screen SPI parameters */
 127 static struct pl022_config_chip spi0_chip_info = {
 128         .lbm                    = LOOPBACK_DISABLED,
 129         .com_mode               = INTERRUPT_TRANSFER,
 130         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
 131         .hierarchy              = SSP_MASTER,
 132         .slave_tx_disable       = 0,
 133         .endian_tx              = SSP_TX_LSB,
 134         .endian_rx              = SSP_RX_LSB,
 135         .data_size              = SSP_DATA_BITS_8,
 136         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
 137         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
 138         .clk_phase              = SSP_CLK_FIRST_EDGE,
 139         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
 140         .ctrl_len               = SSP_BITS_8,
 141         .wait_state             = SSP_MWIRE_WAIT_ZERO,
 142         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
 143         .cs_control             = ea3250_spi_cs_set,
 144 };
 145
 146 /* Touch screen interrupt status function */
 147 static int ea3250_ads7846_pendown_state(void)
 148 {
 149         u32 tmp = gpio_get_value(ADS_TS_GPIO);
 150         return (tmp == 0);
 151 }
 152
 153 /* Touch screen platform data */
 154 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
 155         .debounce_max   = 10,
 156         .debounce_tol   = 3,
 157         .pressure_max   = 1024,
 158         .get_pendown_state = ea3250_ads7846_pendown_state,
 159 };
 160
 161 /*
 162  * SPI based LCDC data
 163  */
 164 /* LCDC chip select function */
 165 static void ea3250_spi_lcdc_cs_set(u32 control)
 166 {
 167         gpio_set_value(LCD_CS_GPIO, (int) control);
 168 }
 169
 170 /* LCDC SPI parameters */
 171 static struct pl022_config_chip spi0_chip_info1 = {
 172         .lbm                    = LOOPBACK_DISABLED,
 173         .com_mode               = INTERRUPT_TRANSFER,
 174         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
 175         .hierarchy              = SSP_MASTER,
 176         .slave_tx_disable       = 0,
 177         .endian_tx              = SSP_TX_LSB,
 178         .endian_rx              = SSP_RX_LSB,
 179         .data_size              = SSP_DATA_BITS_8,
 180         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
 181         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
 182         .clk_phase              = SSP_CLK_FIRST_EDGE,
 183         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
 184         .ctrl_len               = SSP_BITS_8,
 185         .wait_state             = SSP_MWIRE_WAIT_ZERO,
 186         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
 187         .cs_control             = ea3250_spi_lcdc_cs_set,
 188 };
 189
 190 /* SPI devices registration */
 191 static int __init ea3250_spi_devices_register(void)
 192 {
 193 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 194         static struct spi_board_info info[] = {
 195                 {
 196                         .modalias = "spidev",
 197                         .max_speed_hz = 2500000,
 198                         .bus_num = 0,
 199                         .chip_select = 0,
 200                         .controller_data = &spi0_chip_info,
 201                 },
 202         };
 203 #else
 204         struct spi_board_info info[] = {
 205                 {
 206                         .modalias      = "ads7846",
 207                         .max_speed_hz  = 2500000,
 208                         .chip_select   = 0,
 209                         .irq           = IRQ_LPC32XX_GPIO_00,
 210                         .platform_data = &ea_ads7846_platform_data,
 211                         .controller_data = &spi0_chip_info,
 212                 },
 213                 {
 214                         .modalias      = "ea3250_lcdc",
 215                         .max_speed_hz  = 10000000,
 216                         .chip_select   = 1,
 217                         .controller_data = &spi0_chip_info1,
 218                 },
 219         };
 220 #endif
 221
 222         /* Configure ADS TS INT GPIO pin as input */
 223         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
 224                 return -EIO;
 225         if(gpio_direction_input(ADS_TS_GPIO))
 226                 return -EIO;
 227
 228         /* Configure LCDC CS GPIO pin */
 229         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
 230                 return -EIO;
 231         if(gpio_direction_output(LCD_CS_GPIO, 1))
 232                 return -EIO;
 233
 234         return spi_register_board_info(info, ARRAY_SIZE(info));
 235 }
 236 arch_initcall(ea3250_spi_devices_register);
 237
 238 /*
 239  * LCDC AMBA Driver Board Functions
 240  */
 241 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
 242 /*
 243  * Support for Embedded Artists 3.2 inch QVGA LCD panel
 244  */
 245 static struct clcd_panel conn_lcd_panel = {
 246         .mode           = {
 247                 .name           = "QVGA portrait",
 248                 .refresh        = 60,
 249                 .xres           = 240,
 250                 .yres           = 320,
 251                 .pixclock       = 121654,
 252                 .left_margin    = 28,
 253                 .right_margin   = 10,
 254                 .upper_margin   = 2,
 255                 .lower_margin   = 2,
 256                 .hsync_len      = 2,
 257                 .vsync_len      = 2,
 258                 .sync           = 0,
 259                 .vmode          = FB_VMODE_NONINTERLACED,
 260         },
 261         .width          = -1,
 262         .height         = -1,
 263         .tim2           = (TIM2_IVS | TIM2_IHS),
 264         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
 265                                 CNTL_LCDBPP16_565),
 266         .bpp            = 16,
 267 };
 268
 269 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
 270 /*
 271  * Support for Embedded Artists 2.8 inch QVGA OLED panel
 272 */
 273 static struct clcd_panel conn_lcd_panel = {
 274         .mode           = {
 275                 .name           = "QVGA portrait",
 276                 .refresh        = 60,
 277                 .xres           = 240,
 278                 .yres           = 320,
 279                 .pixclock       = 176366,
 280                 .left_margin    = 33,
 281                 .right_margin   = 26,
 282                 .upper_margin   = 3,
 283                 .lower_margin   = 8,
 284                 .hsync_len      = 32,
 285                 .vsync_len      = 4,
 286                 .sync           = 0,
 287                 .vmode          = FB_VMODE_NONINTERLACED,
 288         },
 289         .width          = -1,
 290         .height         = -1,
 291         .tim2           = (TIM2_IVS | TIM2_IHS),
 292         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
 293                                 CNTL_LCDBPP16_565),
 294         .bpp            = 16,
 295 };
 296 #endif
 297
 298 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
 299 {
 300         dma_addr_t dma;
 301
 302         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
 303                         PANEL_SIZE, &dma, GFP_KERNEL);
 304         if (!fb->fb.screen_base) {
 305                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 306                 return -ENOMEM;
 307         }
 308
 309         fb->fb.fix.smem_start = dma;
 310         fb->fb.fix.smem_len = PANEL_SIZE;
 311         fb->panel = &conn_lcd_panel;
 312
 313         /* Configure LCDC RS GPIO pin */
 314         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
 315                 return -EIO;
 316
 317         if(gpio_direction_output(LCD_RS_GPIO, 1))
 318                 return -EIO;
 319
 320         /* Configure LCDC Backlight GPIO pin */
 321         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
 322                 return -EIO;
 323
 324 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
 325         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
 326 #else
 327         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
 328 #endif
 329                 return -EIO;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 336 {
 337         return dma_mmap_writecombine(&fb->dev->dev, vma,
 338                                      fb->fb.screen_base,
 339                                      fb->fb.fix.smem_start,
 340                                      fb->fb.fix.smem_len);
 341 }
 342
 343 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
 344 {
 345         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 346                               fb->fb.screen_base, fb->fb.fix.smem_start);
 347 }
 348
 349 static void spiSend(u8 *buf, size_t len)
 350 {
 351         BUG_ON(ea3250_spi_lcd_dev == NULL);
 352         spi_write(ea3250_spi_lcd_dev, buf, len);
 353 }
 354
 355 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
 356 static void writeToDisp(u16 data)
 357 {
 358         u8 buf[3];
 359
 360         /* Initiliase buffer */
 361         buf[0] = 0x72;
 362         buf[1] = data >> 8;
 363         buf[2] = data & 0xff;
 364         spiSend(buf, 3);
 365 }
 366 #endif
 367
 368 static void writeToReg(u16 addr, u16 data)
 369 {
 370         u8 buf[3];
 371
 372 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
 373         RESET_RS;
 374         buf[0] = 0x00;
 375         buf[1] = addr & 0xff;
 376         spiSend(buf, 2);
 377
 378         SET_RS;
 379         buf[0] = data >> 8;
 380         buf[1] = data & 0xff;
 381         spiSend(buf, 2);
 382
 383         RESET_RS;
 384         buf[0] = 0x00;
 385         buf[1] = 0x22;
 386         spiSend(buf, 2);
 387 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
 388         buf[0] = 0x70;
 389         buf[1] = data >> 8;
 390         buf[2] = data & 0xff;
 391         spiSend(buf, 3);
 392 #endif
 393
 394 }
 395
 396 static void clcd_display_init(void)
 397 {
 398         u32 tmp;
 399
 400         /* setup MUX register to use SSP0 */
 401         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
 402         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
 403
 404 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
 405
 406         writeToReg (0x00,0x0001);
 407         mdelay(20);
 408         writeToReg (0x03,0xA2A4);
 409         writeToReg (0x0C,0x0004);
 410         writeToReg (0x0D,0x0308);
 411         writeToReg (0x0E,0x3000);
 412         mdelay(50);
 413         writeToReg (0x1E,0x00AF);
 414         writeToReg (0x01,0x2B3F);
 415         writeToReg (0x02,0x0600);
 416         writeToReg (0x10,0x0000);
 417         writeToReg (0x07,0x0233);
 418         writeToReg (0x0B,0x0039);
 419         writeToReg (0x0F,0x0000);
 420         mdelay(50);
 421
 422         writeToReg (0x30,0x0707);
 423         writeToReg (0x31,0x0204);
 424         writeToReg (0x32,0x0204);
 425         writeToReg (0x33,0x0502);
 426         writeToReg (0x34,0x0507);
 427         writeToReg (0x35,0x0204);
 428         writeToReg (0x36,0x0204);
 429         writeToReg (0x37,0x0502);
 430         writeToReg (0x3A,0x0302);
 431         writeToReg (0x3B,0x0302);
 432
 433         writeToReg (0x23,0x0000);
 434         writeToReg (0x24,0x0000);
 435
 436         writeToReg (0x48,0x0000);
 437         writeToReg (0x49,0x013F);
 438         writeToReg (0x4A,0x0000);
 439         writeToReg (0x4B,0x0000);
 440
 441         writeToReg (0x41,0x0000);
 442         writeToReg (0x42,0x0000);
 443
 444         writeToReg (0x44,0xEF00);
 445         writeToReg (0x45,0x0000);
 446         writeToReg (0x46,0x013F);
 447         mdelay(50);
 448
 449         writeToReg (0x44,0xEF00);
 450         writeToReg (0x45,0x0000);
 451         writeToReg (0x4E,0x0000);
 452         writeToReg (0x4F,0x0000);
 453         writeToReg (0x46,0x013F);
 454
 455 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
 456
 457         writeToReg(0,0x02);
 458         writeToDisp(0x0192);
 459
 460         writeToReg(0,0x03);
 461         writeToDisp(0x0130);
 462
 463         /* set standby off */
 464         writeToReg(0,0x10);
 465         writeToDisp(0x0000);
 466
 467         mdelay(100);
 468
 469         /* set display on */
 470         writeToReg(0,0x05);
 471         writeToDisp(0x0001);
 472
 473         /* enable image data transfer */
 474         writeToReg(0,0x22);
 475 #endif
 476 }
 477
 478 void clcd_disable(struct clcd_fb *fb)
 479 {
 480         /* Disable the backlight */
 481 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
 482         gpio_set_value(BKL_POW_GPIO, 1);
 483 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
 484         gpio_set_value(BKL_POW_GPIO, 0);
 485 #endif
 486 }
 487
 488 void clcd_enable(struct clcd_fb *fb)
 489 {
 490         clcd_display_init();
 491
 492         /* Enable the backlight */
 493 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
 494         gpio_set_value(BKL_POW_GPIO, 0);
 495 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
 496         gpio_set_value(BKL_POW_GPIO, 1);
 497 #endif
 498
 499 }
 500
 501 struct clcd_board lpc32xx_clcd_data = {
 502 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
 503         .name           = "Embedded Artists 3.2 inch LCD",
 504 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
 505         .name           = "Embedded Artists 2.8 inch OLED",
 506 #else
 507         .name           = "Unknown Display",
 508 #endif
 509         .check          = clcdfb_check,
 510         .decode         = clcdfb_decode,
 511         .disable        = clcd_disable,
 512         .enable         = clcd_enable,
 513         .setup          = lpc32xx_clcd_setup,
 514         .mmap           = lpc32xx_clcd_mmap,
 515         .remove         = lpc32xx_clcd_remove,
 516 };
 517
 518 struct amba_device lpc32xx_clcd_device = {
 519         .dev                            = {
 520                 .coherent_dma_mask      = ~0,
 521                 .init_name              = "dev:clcd",
 522                 .platform_data          = &lpc32xx_clcd_data,
 523         },
 524         .res                            = {
 525                 .start                  = LPC32XX_LCD_BASE,
 526                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
 527                 .flags                  = IORESOURCE_MEM,
 528         },
 529         .dma_mask                       = ~0,
 530         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
 531 };
 532
 533 /*
 534  * SPI LCDC Driver Probe function
 535  */
 536 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
 537 {
 538         int err;
 539
 540         spi->mode = SPI_MODE_0;
 541         ea3250_spi_lcd_dev = spi;
 542
 543         /* SPI settings */
 544         err = spi_setup(spi);
 545         if (err < 0) {
 546                 dev_err(&spi->dev, "Err in setting SPI \n");
 547                 return err;
 548         }
 549         return 0;
 550 }
 551
 552 /*
 553  *  * SPI LCDC Driver remove function
 554  *   * */
 555 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
 556 {
 557         return 0;
 558 }
 559
 560 static struct spi_driver ea3250_spi_lcdc_driver = {
 561         .driver = {
 562                 .name   = "ea3250_lcdc",
 563                 .bus    = &spi_bus_type,
 564                 .owner  = THIS_MODULE,
 565         },
 566         .probe  = ea3250_spi_lcdc_probe,
 567         .remove = __devexit_p(ea3250_spi_lcdc_remove),
 568 };
 569
 570 void __init ea3250_spi_lcdc_drv_init(void)
 571 {
 572         spi_register_driver(&ea3250_spi_lcdc_driver);
 573 }
 574
 575 /* AMBA based devices list */
 576 static struct amba_device *amba_devs[] __initdata = {
 577         &lpc32xx_ssp0_device,
 578         &lpc32xx_clcd_device,
 579 };
 580
 581 /*
 582  * Register AMBA BUS Devices.
 583  * Call AMBA device restration after SPI driver probe(),
 584  * as LCD controller uses SPI driver for initialization
 585  */
 586 static int __init ea3250_amba_devices_register(void)
 587 {
 588         u32 i = 0;
 589
 590         /* Add AMBA devices */
 591         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 592                 struct amba_device *d = amba_devs[i];
 593                 amba_device_register(d, &iomem_resource);
 594         }
 595
 596         return 0;
 597 }
 598 device_initcall_sync(ea3250_amba_devices_register);
 599
 600 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
 601 /*
 602  *  * Board specific NAND setup data
 603  *   */
 604 static int nandwp_enable(int enable)
 605 {
 606         if (enable != 0)
 607                 gpio_set_value(NAND_WP_GPIO,0);
 608         else
 609                 gpio_set_value(NAND_WP_GPIO,1);
 610
 611         return 1;
 612 }
 613 #define BLK_SIZE (1024 * 128)
 614 static struct mtd_partition __initdata ea3250_nand_partition[] = {
 615         {
 616                 .name   = "ea3250-boot",
 617                 .offset = 0,
 618                 .size   = (BLK_SIZE * 7)
 619         },
 620         {
 621                 .name   = "ea3250-ubt-prms",
 622                 .offset = MTDPART_OFS_APPEND,
 623                 .size   = (BLK_SIZE * 1)
 624         },
 625         {
 626                 .name   = "ea3250-kernel",
 627                 .offset = MTDPART_OFS_APPEND,
 628                 .size   = (BLK_SIZE * 32)
 629         },
 630         {
 631                 .name   = "ea3250-rootfs",
 632                 .offset = MTDPART_OFS_APPEND,
 633                 .size   = (BLK_SIZE * 40)
 634         },
 635         {
 636                 .name   = "ea3250-jffs2",
 637                 .offset = MTDPART_OFS_APPEND,
 638                 .size   = MTDPART_SIZ_FULL
 639         },
 640 };
 641 static struct mtd_partition * __init ea3250_nand_partitions(int size, int *num_partitions)
 642 {
 643         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
 644         return ea3250_nand_partition;
 645 }
 646 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
 647 {
 648         .wdr_clks               = 14,
 649         .wwidth                 = 260000000,
 650         .whold                  = 104000000,
 651         .wsetup                 = 200000000,
 652         .rdr_clks               = 14,
 653         .rwidth                 = 34666666,
 654         .rhold                  = 104000000,
 655         .rsetup                 = 200000000,
 656         .use16bus               = 0,
 657         .enable_write_prot      = nandwp_enable,
 658         .partition_info         = ea3250_nand_partitions,
 659 };
 660
 661 /*
 662  *  * SLC NAND resources
 663  *   */
 664 static struct resource slc_nand_resources[] = {
 665         [0] = {
 666                 .start  = LPC32XX_SLC_BASE,
 667                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
 668                 .flags  = IORESOURCE_MEM,
 669         },
 670
 671         [1] = {
 672                 .start  = IRQ_LPC32XX_FLASH,
 673                 .end    = IRQ_LPC32XX_FLASH,
 674                 .flags  = IORESOURCE_IRQ,
 675         },
 676
 677 };
 678 static struct platform_device lpc32xx_slc_nand_device = {
 679         .name           = "lpc32xx-nand",
 680         .id             = 0,
 681         .dev            = {
 682                                 .platform_data  = &lpc32xx_nandcfg,
 683         },
 684         .num_resources  = ARRAY_SIZE(slc_nand_resources),
 685         .resource       = slc_nand_resources,
 686 };
 687 #endif
 688
 689 /*
 690  * Network Support
 691  */
 692 static struct lpc_net_cfg lpc32xx_netdata =
 693 {
 694         .phy_irq        = -1,
 695         .phy_mask       = 0xFFFFFFF0,
 696 };
 697
 698 static struct resource net_resources[] = {
 699         [0] = {
 700                 .start  = LPC32XX_ETHERNET_BASE,
 701                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
 702                 .flags  = IORESOURCE_MEM,
 703         },
 704
 705         [1] = {
 706                 .start  = IRQ_LPC32XX_ETHERNET,
 707                 .end    = IRQ_LPC32XX_ETHERNET,
 708                 .flags  = IORESOURCE_IRQ,
 709         },
 710
 711 };
 712
 713 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
 714 static struct platform_device lpc32xx_net_device = {
 715         .name           = "lpc-net",
 716         .id             = 0,
 717         .dev            = {
 718                 .dma_mask = &lpc32xx_mac_dma_mask,
 719                 .coherent_dma_mask = 0xffffffffUL,
 720                 .platform_data  = &lpc32xx_netdata,
 721         },
 722         .num_resources  = ARRAY_SIZE(net_resources),
 723         .resource       = net_resources,
 724 };
 725
 726 /*
 727  * I2C devices support
 728  */
 729 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
 730         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
 731 #if defined (CONFIG_SENSORS_PCA9532)
 732                 {
 733                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
 734
 735                 },
 736 #endif
 737 #if defined (CONFIG_AT24)
 738                 {
 739                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
 740                 },
 741 #endif
 742         };
 743 #endif
 744
 745 static struct platform_device* ea3250_devs[] __initdata = {
 746         &lpc32xx_i2c0_device,
 747         &lpc32xx_i2c1_device,
 748         &lpc32xx_i2c2_device,
 749         &lpc32xx_watchdog_device,
 750         &lpc32xx_gpio_led_device,
 751         &lpc32xx_rtc_device,
 752         &lpc32xx_net_device,
 753 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
 754         &lpc32xx_slc_nand_device,
 755 #endif
 756 #if defined(CONFIG_USB_OHCI_HCD)
 757         &lpc32xx_ohci_device,
 758 #endif
 759 #if defined(CONFIG_USB_GADGET_LPC32XX)
 760         &lpc32xx_usbd_device,
 761 #endif
 762 };
 763
 764 extern void __init ea3250_spi_lcdc_drv_init(void);
 765
 766 /*
 767  * Board specific functions
 768  */
 769 void __init ea3250_board_init(void)
 770 {
 771         u32 tmp;
 772
 773         /* Intiliase GPIO */
 774         lpc32xx_gpio_init();
 775
 776         /* Set SPI CS GPIO to output */
 777         gpio_request(SPI0_CS_GPIO, "spi0 cs");
 778         gpio_direction_output(SPI0_CS_GPIO, 1);
 779
 780         /* Setup network interface for RMII mode */
 781         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
 782         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
 783         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
 784         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
 785
 786         /* Setup SLC NAND controller */
 787         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
 788                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
 789
 790         /* Setup LCD muxing to RGB565 */
 791         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
 792                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
 793                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
 794         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
 795         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 796
 797         /* Set up I2C pull levels */
 798         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
 799         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
 800                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
 801         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
 802
 803         /* Enable DMA for I2S1 channel */
 804         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
 805         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
 806         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
 807
 808         /* Initalise Serial device */
 809         lpc32xx_serial_init();
 810
 811         /*
 812          * AMBA peripheral clocks need to be enabled prior to AMBA device
 813          * detection or a data fault will occur, so enable the clocks
 814          * here. However, we don't want to enable them if the peripheral
 815          * isn't included in the image
 816          */
 817         /* Initialise SSP clock */
 818         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
 819         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
 820                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
 821
 822         /* Initialise LCD clock */
 823         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 824         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
 825                         LPC32XX_CLKPWR_LCDCLK_CTRL);
 826
 827         /* Enable SD card clock so AMBA driver will work correctly. The
 828            AMBA driver needs the clock before the SD card controller
 829            driver initializes it. The clock will turn off once the driver
 830            has been initialized. */
 831         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 832         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
 833                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
 834         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 835
 836         /* Disable UART5->USB transparent mode or USB won't work */
 837         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
 838         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
 839         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
 840
 841         /* Add platform devcies */
 842         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
 843
 844         /* Register SPI driver */
 845         ea3250_spi_lcdc_drv_init();
 846
 847         /* Test clock needed for UDA1380 initial init */
 848         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
 849                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
 850                         LPC32XX_CLKPWR_TEST_CLK_SEL);
 851
 852 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
 853         i2c_register_board_info(0, ea3250_i2c_board_info,
 854                         ARRAY_SIZE(ea3250_i2c_board_info));
 855 #endif
 856 }
 857
 858 static int __init lpc32xx_display_uid(void)
 859 {
 860         u32 uid[4];
 861
 862         lpc32xx_get_uid(uid);
 863
 864         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
 865                         uid[3], uid[2], uid[1], uid[0]);
 866
 867         return 1;
 868 }
 869 arch_initcall(lpc32xx_display_uid);
 870
 871 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
 872         /* Maintainer: Embedded Artists */
 873         .phys_io        = LPC32XX_UART5_BASE,
 874         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
 875         .boot_params    = 0x80000100,
 876         .map_io         = lpc32xx_map_io,
 877         .init_irq       = lpc32xx_init_irq,
 878         .timer          = &lpc32xx_timer,
 879         .init_machine   = ea3250_board_init,
 880         MACHINE_END
 881
 882 /* For backwards compatibility with older bootloaders only */
 883 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
 884         /* Maintainer: Embedded Artists */
 885         .phys_io        = LPC32XX_UART5_BASE,
 886         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
 887         .boot_params    = 0x80000100,
 888         .map_io         = lpc32xx_map_io,
 889         .init_irq       = lpc32xx_init_irq,
 890         .timer          = &lpc32xx_timer,
 891         .init_machine   = ea3250_board_init,
 892         MACHINE_END