Add support for the SD card to the Embedded Artist EA3250 board
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / ea3250.c
1 /*
2  * arch/arm/mach-lpc32xx/ea3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/gpio.h>
29 #include <linux/input.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl022.h>
33 #include <linux/amba/mmci.h>
34 #include <mtd/mtd-abi.h>
35
36 #include <asm/setup.h>
37 #include <asm/mach-types.h>
38 #include <asm/mach/arch.h>
39
40 #include <mach/hardware.h>
41 #include <mach/platform.h>
42 #include <mach/board.h>
43 #include "common.h"
44
45 #include <linux/spi/ads7846.h>
46
47 #define I2C_PCA9532_ADDR 0x60
48 #define I2C_24LC256_ADDR 0x50
49
50 /*
51  * Mapped GPIOLIB GPIOs
52  */
53 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
54 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
55 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
56 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
57 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
58 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
59 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
60 #define SSEL0_GPIO5     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
61 #define MMC_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
62
63 /*
64  * LCD controller functions
65  */
66 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
67 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
68 #define PANEL_SIZE      (3 * SZ_64K)
69
70 /* SPI LCDC device structure */
71 struct spi_device *ea3250_spi_lcd_dev = NULL;
72
73 /*
74  * Tick LED
75  */
76 static struct gpio_led phy_leds[] = {
77         {
78                 .name                   = "led0",
79                 .gpio                   = LED_GPIO,
80                 .active_low             = 1,
81                 .default_trigger        = "heartbeat",
82         },
83 };
84
85 static struct gpio_led_platform_data led_data = {
86         .leds = phy_leds,
87         .num_leds = ARRAY_SIZE(phy_leds),
88 };
89
90 static struct platform_device lpc32xx_gpio_led_device = {
91         .name                   = "leds-gpio",
92         .id                     = -1,
93         .dev.platform_data      = &led_data,
94 };
95
96 /*
97  * AMBA SSP (SPI)
98  */
99 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
100         .bus_id                 = 0,
101         .num_chipselect         = 2,
102         .enable_dma             = 0,
103 };
104
105 static struct amba_device lpc32xx_ssp0_device = {
106         .dev    = {
107                 .coherent_dma_mask      = ~0,
108                 .init_name              = "dev:ssp0",
109                 .platform_data          = &lpc32xx_ssp0_data,
110         },
111         .res                            = {
112                 .start                  = LPC32XX_SSP0_BASE,
113                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
114                 .flags                  = IORESOURCE_MEM,
115         },
116         .dma_mask                       = ~0,
117         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
118 };
119
120 /*
121  * Touchscreen device
122  */
123 /* Touch screen chip select function */
124 static void ea3250_spi_cs_set(u32 control)
125 {
126         gpio_set_value(SPI0_CS_GPIO, (int) control);
127 }
128
129 /* Touch screen SPI parameters */
130 static struct pl022_config_chip spi0_chip_info = {
131         .lbm                    = LOOPBACK_DISABLED,
132         .com_mode               = INTERRUPT_TRANSFER,
133         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
134         .hierarchy              = SSP_MASTER,
135         .slave_tx_disable       = 0,
136         .endian_tx              = SSP_TX_LSB,
137         .endian_rx              = SSP_RX_LSB,
138         .data_size              = SSP_DATA_BITS_8,
139         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
140         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
141         .clk_phase              = SSP_CLK_FIRST_EDGE,
142         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
143         .ctrl_len               = SSP_BITS_8,
144         .wait_state             = SSP_MWIRE_WAIT_ZERO,
145         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
146         .cs_control             = ea3250_spi_cs_set,
147 };
148
149 /* Touch screen interrupt status function */
150 static int ea3250_ads7846_pendown_state(void)
151 {
152         u32 tmp = gpio_get_value(ADS_TS_GPIO);
153         return (tmp == 0);
154 }
155
156 /* Touch screen platform data */
157 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
158         .debounce_max   = 10,
159         .debounce_tol   = 3,
160         .pressure_max   = 1024,
161         .get_pendown_state = ea3250_ads7846_pendown_state,
162 };
163
164 /*
165  * SPI based LCDC data
166  */
167 /* LCDC chip select function */
168 static void ea3250_spi_lcdc_cs_set(u32 control)
169 {
170         gpio_set_value(LCD_CS_GPIO, (int) control);
171 }
172
173 /* LCDC SPI parameters */
174 static struct pl022_config_chip spi0_chip_info1 = {
175         .lbm                    = LOOPBACK_DISABLED,
176         .com_mode               = INTERRUPT_TRANSFER,
177         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
178         .hierarchy              = SSP_MASTER,
179         .slave_tx_disable       = 0,
180         .endian_tx              = SSP_TX_LSB,
181         .endian_rx              = SSP_RX_LSB,
182         .data_size              = SSP_DATA_BITS_8,
183         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
184         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
185         .clk_phase              = SSP_CLK_FIRST_EDGE,
186         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
187         .ctrl_len               = SSP_BITS_8,
188         .wait_state             = SSP_MWIRE_WAIT_ZERO,
189         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
190         .cs_control             = ea3250_spi_lcdc_cs_set,
191 };
192
193 /* SPI devices registration */
194 static int __init ea3250_spi_devices_register(void)
195 {
196 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
197         static struct spi_board_info info[] = {
198                 {
199                         .modalias = "spidev",
200                         .max_speed_hz = 2500000,
201                         .bus_num = 0,
202                         .chip_select = 0,
203                         .controller_data = &spi0_chip_info,
204                 },
205         };
206 #else
207         struct spi_board_info info[] = {
208                 {
209                         .modalias      = "ads7846",
210                         .max_speed_hz  = 2500000,
211                         .chip_select   = 0,
212                         .irq           = IRQ_LPC32XX_GPIO_00,
213                         .platform_data = &ea_ads7846_platform_data,
214                         .controller_data = &spi0_chip_info,
215                 },
216                 {
217                         .modalias      = "ea3250_lcdc",
218                         .max_speed_hz  = 10000000,
219                         .chip_select   = 1,
220                         .controller_data = &spi0_chip_info1,
221                 },
222         };
223 #endif
224
225         /* Configure ADS TS INT GPIO pin as input */
226         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
227                 return -EIO;
228         if(gpio_direction_input(ADS_TS_GPIO))
229                 return -EIO;
230
231         /* Configure LCDC CS GPIO pin */
232         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
233                 return -EIO;
234         if(gpio_direction_output(LCD_CS_GPIO, 1))
235                 return -EIO;
236
237         return spi_register_board_info(info, ARRAY_SIZE(info));
238 }
239 arch_initcall(ea3250_spi_devices_register);
240
241 #if defined (CONFIG_FB_ARMCLCD)
242 /*
243  * LCDC AMBA Driver Board Functions
244  */
245 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
246 /*
247  * Support for Embedded Artists 3.2 inch QVGA LCD panel
248  */
249 static struct clcd_panel conn_lcd_panel = {
250         .mode           = {
251                 .name           = "QVGA portrait",
252                 .refresh        = 60,
253                 .xres           = 240,
254                 .yres           = 320,
255                 .pixclock       = 121654,
256                 .left_margin    = 28,
257                 .right_margin   = 10,
258                 .upper_margin   = 2,
259                 .lower_margin   = 2,
260                 .hsync_len      = 3,
261                 .vsync_len      = 2,
262                 .sync           = 0,
263                 .vmode          = FB_VMODE_NONINTERLACED,
264         },
265         .width          = -1,
266         .height         = -1,
267         .tim2           = (TIM2_IVS | TIM2_IHS),
268         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
269                                 CNTL_LCDBPP16_565),
270         .bpp            = 16,
271 };
272
273 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
274 /*
275  * Support for Embedded Artists 2.8 inch QVGA OLED panel
276 */
277 static struct clcd_panel conn_lcd_panel = {
278         .mode           = {
279                 .name           = "QVGA portrait",
280                 .refresh        = 60,
281                 .xres           = 240,
282                 .yres           = 320,
283                 .pixclock       = 176366,
284                 .left_margin    = 33,
285                 .right_margin   = 26,
286                 .upper_margin   = 3,
287                 .lower_margin   = 8,
288                 .hsync_len      = 32,
289                 .vsync_len      = 4,
290                 .sync           = 0,
291                 .vmode          = FB_VMODE_NONINTERLACED,
292         },
293         .width          = -1,
294         .height         = -1,
295         .tim2           = (TIM2_IVS | TIM2_IHS),
296         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
297                                 CNTL_LCDBPP16_565),
298         .bpp            = 16,
299 };
300 #endif
301
302 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
303 {
304         dma_addr_t dma;
305
306         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
307                         PANEL_SIZE, &dma, GFP_KERNEL);
308         if (!fb->fb.screen_base) {
309                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
310                 return -ENOMEM;
311         }
312
313         fb->fb.fix.smem_start = dma;
314         fb->fb.fix.smem_len = PANEL_SIZE;
315         fb->panel = &conn_lcd_panel;
316
317         if (gpio_request(SSEL0_GPIO5, "Unused GPIO5 input"))
318                 return -EIO;
319         if(gpio_direction_input(SSEL0_GPIO5))
320                 return -EIO;
321
322         /* Configure LCDC RS GPIO pin */
323         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
324                 return -EIO;
325
326         if(gpio_direction_output(LCD_RS_GPIO, 1))
327                 return -EIO;
328
329         /* Configure LCDC Backlight GPIO pin */
330         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
331                 return -EIO;
332
333 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
334         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
335 #else
336         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
337 #endif
338                 return -EIO;
339         }
340
341         return 0;
342 }
343
344 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
345 {
346         return dma_mmap_writecombine(&fb->dev->dev, vma,
347                                      fb->fb.screen_base,
348                                      fb->fb.fix.smem_start,
349                                      fb->fb.fix.smem_len);
350 }
351
352 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
353 {
354         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
355                               fb->fb.screen_base, fb->fb.fix.smem_start);
356 }
357
358 static void spiSend(u8 *buf, size_t len)
359 {
360         BUG_ON(ea3250_spi_lcd_dev == NULL);
361         spi_write(ea3250_spi_lcd_dev, buf, len);
362 }
363
364 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
365 static void writeToDisp(u16 data)
366 {
367         u8 buf[3];
368
369         /* Initiliase buffer */
370         buf[0] = 0x72;
371         buf[1] = data >> 8;
372         buf[2] = data & 0xff;
373         spiSend(buf, 3);
374 }
375 #endif
376
377 static void writeToReg(u16 addr, u16 data)
378 {
379         u8 buf[3];
380
381 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
382         RESET_RS;
383         buf[0] = 0x00;
384         buf[1] = addr & 0xff;
385         spiSend(buf, 2);
386
387         SET_RS;
388         buf[0] = data >> 8;
389         buf[1] = data & 0xff;
390         spiSend(buf, 2);
391
392         RESET_RS;
393         buf[0] = 0x00;
394         buf[1] = 0x22;
395         spiSend(buf, 2);
396 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
397         buf[0] = 0x70;
398         buf[1] = data >> 8;
399         buf[2] = data & 0xff;
400         spiSend(buf, 3);
401 #endif
402
403 }
404
405 static void clcd_display_init(void)
406 {
407         u32 tmp;
408
409         /* setup MUX register to use SSP0 */
410         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
411         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
412
413 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
414
415         writeToReg (0x00,0x0001);
416         mdelay(20);
417         writeToReg (0x03,0xA2A4);
418         writeToReg (0x0C,0x0004);
419         writeToReg (0x0D,0x0308);
420         writeToReg (0x0E,0x3000);
421         mdelay(50);
422         writeToReg (0x1E,0x00AF);
423         writeToReg (0x01,0x2B3F);
424         writeToReg (0x02,0x0600);
425         writeToReg (0x10,0x0000);
426         writeToReg (0x07,0x0233);
427         writeToReg (0x0B,0x0039);
428         writeToReg (0x0F,0x0000);
429         mdelay(50);
430
431         writeToReg (0x30,0x0707);
432         writeToReg (0x31,0x0204);
433         writeToReg (0x32,0x0204);
434         writeToReg (0x33,0x0502);
435         writeToReg (0x34,0x0507);
436         writeToReg (0x35,0x0204);
437         writeToReg (0x36,0x0204);
438         writeToReg (0x37,0x0502);
439         writeToReg (0x3A,0x0302);
440         writeToReg (0x3B,0x0302);
441
442         writeToReg (0x23,0x0000);
443         writeToReg (0x24,0x0000);
444
445         writeToReg (0x48,0x0000);
446         writeToReg (0x49,0x013F);
447         writeToReg (0x4A,0x0000);
448         writeToReg (0x4B,0x0000);
449
450         writeToReg (0x41,0x0000);
451         writeToReg (0x42,0x0000);
452
453         writeToReg (0x44,0xEF00);
454         writeToReg (0x45,0x0000);
455         writeToReg (0x46,0x013F);
456         mdelay(50);
457
458         writeToReg (0x44,0xEF00);
459         writeToReg (0x45,0x0000);
460         writeToReg (0x4E,0x0000);
461         writeToReg (0x4F,0x0000);
462         writeToReg (0x46,0x013F);
463
464 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
465
466         writeToReg(0,0x02);
467         writeToDisp(0x0192);
468
469         writeToReg(0,0x03);
470         writeToDisp(0x0130);
471
472         /* set standby off */
473         writeToReg(0,0x10);
474         writeToDisp(0x0000);
475
476         mdelay(100);
477
478         /* set display on */
479         writeToReg(0,0x05);
480         writeToDisp(0x0001);
481
482         /* enable image data transfer */
483         writeToReg(0,0x22);
484 #endif
485 }
486
487 void clcd_disable(struct clcd_fb *fb)
488 {
489         /* Disable the backlight */
490 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
491         gpio_set_value(BKL_POW_GPIO, 1);
492 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
493         gpio_set_value(BKL_POW_GPIO, 0);
494 #endif
495 }
496
497 void clcd_enable(struct clcd_fb *fb)
498 {
499         clcd_display_init();
500
501         /* Enable the backlight */
502 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
503         gpio_set_value(BKL_POW_GPIO, 0);
504 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
505         gpio_set_value(BKL_POW_GPIO, 1);
506 #endif
507
508 }
509
510 struct clcd_board lpc32xx_clcd_data = {
511 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
512         .name           = "Embedded Artists 3.2 inch LCD",
513 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
514         .name           = "Embedded Artists 2.8 inch OLED",
515 #else
516         .name           = "Unknown Display",
517 #endif
518         .check          = clcdfb_check,
519         .decode         = clcdfb_decode,
520         .disable        = clcd_disable,
521         .enable         = clcd_enable,
522         .setup          = lpc32xx_clcd_setup,
523         .mmap           = lpc32xx_clcd_mmap,
524         .remove         = lpc32xx_clcd_remove,
525 };
526
527 struct amba_device lpc32xx_clcd_device = {
528         .dev                            = {
529                 .coherent_dma_mask      = ~0,
530                 .init_name              = "dev:clcd",
531                 .platform_data          = &lpc32xx_clcd_data,
532         },
533         .res                            = {
534                 .start                  = LPC32XX_LCD_BASE,
535                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
536                 .flags                  = IORESOURCE_MEM,
537         },
538         .dma_mask                       = ~0,
539         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
540 };
541 #endif
542
543 /*
544  * SPI LCDC Driver Probe function
545  */
546 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
547 {
548         int err;
549
550         spi->mode = SPI_MODE_0;
551         ea3250_spi_lcd_dev = spi;
552
553         /* SPI settings */
554         err = spi_setup(spi);
555         if (err < 0) {
556                 dev_err(&spi->dev, "Err in setting SPI \n");
557                 return err;
558         }
559         return 0;
560 }
561
562 /*
563  *  * SPI LCDC Driver remove function
564  *   * */
565 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
566 {
567         return 0;
568 }
569
570 static struct spi_driver ea3250_spi_lcdc_driver = {
571         .driver = {
572                 .name   = "ea3250_lcdc",
573                 .bus    = &spi_bus_type,
574                 .owner  = THIS_MODULE,
575         },
576         .probe  = ea3250_spi_lcdc_probe,
577         .remove = __devexit_p(ea3250_spi_lcdc_remove),
578 };
579
580 void __init ea3250_spi_lcdc_drv_init(void)
581 {
582         spi_register_driver(&ea3250_spi_lcdc_driver);
583 }
584
585 #if defined (CONFIG_MMC_ARMMMCI)
586
587 /*
588  * Returns !0 when card is removed, 0 when present
589  */
590 unsigned int mmc_card_detect(struct device *dev)
591 {
592         /*
593          * This function may be adapted to retrieve the actual 'card detect'
594          * status over the I2C bus, from PCA9532 pin 8 (LED4). For now, simply
595          * indicate that a card is always present.
596         */
597         return 0;
598 }
599
600 /*
601  * Enable or disable SD slot power
602  */
603 void mmc_power_enable(int enable)
604 {
605         if (enable != 0)
606         {
607                 /* active low */
608                 gpio_set_value(MMC_POWER_GPIO,0);
609         }
610         else
611         {
612                 gpio_set_value(MMC_POWER_GPIO,0);
613         }
614 }
615
616 /*
617  * Board specific MMC driver data
618  */
619 struct mmci_platform_data lpc32xx_plat_data = {
620         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
621         .translate_vdd  = NULL,
622         .capabilities   = MMC_CAP_4_BIT_DATA,
623         /*
624          * Indicate no direct GPIO, so MMC driver will assume card is NOT
625          * write-protected
626          */
627         .gpio_wp        = -ENOSYS,
628         /*
629          * Indicate no direct GPIO, so MMC driver will call 'status' callback
630          * function
631          */
632         .gpio_cd        = -ENOSYS,
633         /*
634          * Callback function, used by MMC driver in case 'gpio_cd'
635          * equals -ENOSYS
636          */
637         .status         = mmc_card_detect,
638 };
639
640 /*
641  * SD card controller resources
642  */
643 struct amba_device lpc32xx_mmc_device = {
644         .dev                            = {
645                 .coherent_dma_mask      = ~0,
646                 .init_name              = "dev:mmc0",
647                 .platform_data          = &lpc32xx_plat_data,
648         },
649         .res                            = {
650                 .start                  = LPC32XX_SD_BASE,
651                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
652                 .flags                  = IORESOURCE_MEM,
653         },
654         .dma_mask                       = ~0,
655         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
656 };
657 #endif
658
659 /* AMBA based devices list */
660 static struct amba_device *amba_devs[] __initdata = {
661         &lpc32xx_ssp0_device,
662 #if defined (CONFIG_FB_ARMCLCD)
663         &lpc32xx_clcd_device,
664 #endif
665 #if defined (CONFIG_MMC_ARMMMCI)
666         &lpc32xx_mmc_device,
667 #endif
668 };
669
670 /*
671  * Register AMBA BUS Devices.
672  * Call AMBA device restration after SPI driver probe(),
673  * as LCD controller uses SPI driver for initialization
674  */
675 static int __init ea3250_amba_devices_register(void)
676 {
677         u32 i = 0;
678
679         /* Add AMBA devices */
680         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
681                 struct amba_device *d = amba_devs[i];
682                 amba_device_register(d, &iomem_resource);
683         }
684
685         return 0;
686 }
687 device_initcall_sync(ea3250_amba_devices_register);
688
689 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
690 /*
691  *  * Board specific NAND setup data
692  *   */
693 static int nandwp_enable(int enable)
694 {
695         if (enable != 0)
696                 gpio_set_value(NAND_WP_GPIO,0);
697         else
698                 gpio_set_value(NAND_WP_GPIO,1);
699
700         return 1;
701 }
702 #define BLK_SIZE (2048 * 64)
703 static struct mtd_partition ea3250_nand_partition[] = {
704         {
705                 .name   = "ea3250-boot",
706                 .offset = 0,
707                 .size   = (BLK_SIZE * 4),
708                 .mask_flags   = MTD_WRITEABLE,
709         },
710         {
711                 .name   = "ea3250-uboot",
712                 .offset = MTDPART_OFS_APPEND,
713                 .size   = (BLK_SIZE * 6)
714         },
715         {
716                 .name   = "ea3250-kernel",
717                 .offset = MTDPART_OFS_APPEND,
718                 .size   = (BLK_SIZE * 32)
719         },
720         {
721                 .name   = "ea3250-jffs2",
722                 .offset = MTDPART_OFS_APPEND,
723                 .size   = MTDPART_SIZ_FULL
724         },
725 };
726 static struct mtd_partition * ea3250_nand_partitions(int size, int *num_partitions)
727 {
728         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
729         return ea3250_nand_partition;
730 }
731 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
732 {
733         .wdr_clks               = 14,
734         .wwidth                 = 260000000,
735         .whold                  = 104000000,
736         .wsetup                 = 200000000,
737         .rdr_clks               = 14,
738         .rwidth                 = 34666666,
739         .rhold                  = 104000000,
740         .rsetup                 = 200000000,
741         .use_bbt                = true,
742         .polled_completion      = false,
743         .enable_write_prot      = nandwp_enable,
744         .partition_info         = ea3250_nand_partitions,
745 };
746
747 /*
748  *  * SLC NAND resources
749  *   */
750 static struct resource slc_nand_resources[] = {
751         [0] = {
752                 .start  = LPC32XX_SLC_BASE,
753                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
754                 .flags  = IORESOURCE_MEM,
755         },
756
757         [1] = {
758                 .start  = IRQ_LPC32XX_FLASH,
759                 .end    = IRQ_LPC32XX_FLASH,
760                 .flags  = IORESOURCE_IRQ,
761         },
762
763 };
764
765 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
766 static struct platform_device lpc32xx_slc_nand_device = {
767         .name           = "lpc32xx-nand",
768         .id             = 0,
769         .dev            = {
770                                 .platform_data  = &lpc32xx_nandcfg,
771                                 .dma_mask    = &lpc32xx_slc_dma_mask,
772                                 .coherent_dma_mask = ~0UL,
773
774         },
775         .num_resources  = ARRAY_SIZE(slc_nand_resources),
776         .resource       = slc_nand_resources,
777 };
778 #endif
779
780 /*
781  * Network Support
782  */
783 static struct lpc_net_cfg lpc32xx_netdata =
784 {
785         .phy_irq        = -1,
786         .phy_mask       = 0xFFFFFFF0,
787 };
788
789 static struct resource net_resources[] = {
790         [0] = {
791                 .start  = LPC32XX_ETHERNET_BASE,
792                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
793                 .flags  = IORESOURCE_MEM,
794         },
795
796         [1] = {
797                 .start  = IRQ_LPC32XX_ETHERNET,
798                 .end    = IRQ_LPC32XX_ETHERNET,
799                 .flags  = IORESOURCE_IRQ,
800         },
801
802 };
803
804 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
805 static struct platform_device lpc32xx_net_device = {
806         .name           = "lpc-net",
807         .id             = 0,
808         .dev            = {
809                 .dma_mask = &lpc32xx_mac_dma_mask,
810                 .coherent_dma_mask = 0xffffffffUL,
811                 .platform_data  = &lpc32xx_netdata,
812         },
813         .num_resources  = ARRAY_SIZE(net_resources),
814         .resource       = net_resources,
815 };
816
817 /*
818  * I2C devices support
819  */
820 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
821         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
822 #if defined (CONFIG_SENSORS_PCA9532)
823                 {
824                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
825
826                 },
827 #endif
828 #if defined (CONFIG_AT24)
829                 {
830                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
831                 },
832 #endif
833         };
834 #endif
835
836 static struct platform_device* ea3250_devs[] __initdata = {
837         &lpc32xx_i2c0_device,
838         &lpc32xx_i2c1_device,
839         &lpc32xx_i2c2_device,
840         &lpc32xx_watchdog_device,
841         &lpc32xx_gpio_led_device,
842         &lpc32xx_rtc_device,
843         &lpc32xx_net_device,
844 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
845         &lpc32xx_slc_nand_device,
846 #endif
847 #if defined(CONFIG_USB_OHCI_HCD)
848         &lpc32xx_ohci_device,
849 #endif
850 #if defined(CONFIG_USB_GADGET_LPC32XX)
851         &lpc32xx_usbd_device,
852 #endif
853 };
854
855 extern void __init ea3250_spi_lcdc_drv_init(void);
856
857 /*
858  * Board specific functions
859  */
860 void __init ea3250_board_init(void)
861 {
862         u32 tmp;
863
864         /* Intiliase GPIO */
865         lpc32xx_gpio_init();
866
867 #if defined (CONFIG_MMC_ARMMMCI)
868         /* Enable SD slot power */
869         mmc_power_enable(1);
870 #endif
871
872         /* Set SPI CS GPIO to output */
873         gpio_request(SPI0_CS_GPIO, "spi0 cs");
874         gpio_direction_output(SPI0_CS_GPIO, 1);
875
876         /* Setup network interface for RMII mode */
877         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
878         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
879         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
880         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
881
882         /* Setup SLC NAND controller */
883         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
884                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
885
886         /* Setup LCD muxing to RGB565 */
887         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
888                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
889                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
890         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
891         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
892
893         /* Set up I2C pull levels */
894         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
895         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
896                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
897         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
898
899         /* Enable DMA for I2S1 channel */
900         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
901         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
902         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
903
904         /* Initalise Serial device */
905         lpc32xx_serial_init();
906
907         /*
908          * AMBA peripheral clocks need to be enabled prior to AMBA device
909          * detection or a data fault will occur, so enable the clocks
910          * here. However, we don't want to enable them if the peripheral
911          * isn't included in the image
912          */
913         /* Initialise SSP clock */
914         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
915         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
916                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
917
918         /* Initialise LCD clock */
919         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
920         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
921                         LPC32XX_CLKPWR_LCDCLK_CTRL);
922
923         /* Enable SD card clock so AMBA driver will work correctly. The
924            AMBA driver needs the clock before the SD card controller
925            driver initializes it. The clock will turn off once the driver
926            has been initialized. */
927         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
928         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
929                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
930         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
931
932         /* Disable UART5->USB transparent mode or USB won't work */
933         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
934         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
935         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
936
937         /* Add platform devcies */
938         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
939
940         /* Register SPI driver */
941         ea3250_spi_lcdc_drv_init();
942
943         /* Test clock needed for UDA1380 initial init */
944         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
945                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
946                         LPC32XX_CLKPWR_TEST_CLK_SEL);
947
948 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
949         i2c_register_board_info(0, ea3250_i2c_board_info,
950                         ARRAY_SIZE(ea3250_i2c_board_info));
951 #endif
952 }
953
954 static int __init lpc32xx_display_uid(void)
955 {
956         u32 uid[4];
957
958         lpc32xx_get_uid(uid);
959
960         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
961                         uid[3], uid[2], uid[1], uid[0]);
962
963         return 1;
964 }
965 arch_initcall(lpc32xx_display_uid);
966
967 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
968         /* Maintainer: Embedded Artists */
969         .phys_io        = LPC32XX_UART5_BASE,
970         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
971         .boot_params    = 0x80000100,
972         .map_io         = lpc32xx_map_io,
973         .init_irq       = lpc32xx_init_irq,
974         .timer          = &lpc32xx_timer,
975         .init_machine   = ea3250_board_init,
976         MACHINE_END
977
978 /* For backwards compatibility with older bootloaders only */
979 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
980         /* Maintainer: Embedded Artists */
981         .phys_io        = LPC32XX_UART5_BASE,
982         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
983         .boot_params    = 0x80000100,
984         .map_io         = lpc32xx_map_io,
985         .init_irq       = lpc32xx_init_irq,
986         .timer          = &lpc32xx_timer,
987         .init_machine   = ea3250_board_init,
988         MACHINE_END