ARM: LPC32xx: Added missing donfig file and FDI3250 platform file
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / ea3250.c
1 /*
2  * arch/arm/mach-lpc32xx/ea3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/gpio.h>
29 #include <linux/input.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl022.h>
33 #include <linux/amba/mmci.h>
34
35 #include <asm/setup.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38
39 #include <mach/hardware.h>
40 #include <mach/platform.h>
41 #include <mach/board.h>
42 #include "common.h"
43
44 #include <linux/spi/ads7846.h>
45
46 #define I2C_PCA9532_ADDR 0x60
47 #define I2C_24LC256_ADDR 0x50
48
49 /*
50  * Mapped GPIOLIB GPIOs
51  */
52 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
53 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
54 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
55 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
56 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
57 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
58 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
59 #define SSEL0_GPIO5     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
60
61 /*
62  * LCD controller functions
63  */
64 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
65 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
66 #define PANEL_SIZE      (3 * SZ_64K)
67
68 /* SPI LCDC device structure */
69 struct spi_device *ea3250_spi_lcd_dev = NULL;
70
71 /*
72  * Tick LED
73  */
74 static struct gpio_led phy_leds[] = {
75         {
76                 .name                   = "led0",
77                 .gpio                   = LED_GPIO,
78                 .active_low             = 1,
79                 .default_trigger        = "heartbeat",
80         },
81 };
82
83 static struct gpio_led_platform_data led_data = {
84         .leds = phy_leds,
85         .num_leds = ARRAY_SIZE(phy_leds),
86 };
87
88 static struct platform_device lpc32xx_gpio_led_device = {
89         .name                   = "leds-gpio",
90         .id                     = -1,
91         .dev.platform_data      = &led_data,
92 };
93
94 /*
95  * AMBA SSP (SPI)
96  */
97 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
98         .bus_id                 = 0,
99         .num_chipselect         = 2,
100         .enable_dma             = 0,
101 };
102
103 static struct amba_device lpc32xx_ssp0_device = {
104         .dev    = {
105                 .coherent_dma_mask      = ~0,
106                 .init_name              = "dev:ssp0",
107                 .platform_data          = &lpc32xx_ssp0_data,
108         },
109         .res                            = {
110                 .start                  = LPC32XX_SSP0_BASE,
111                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
112                 .flags                  = IORESOURCE_MEM,
113         },
114         .dma_mask                       = ~0,
115         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
116 };
117
118 /*
119  * Touchscreen device
120  */
121 /* Touch screen chip select function */
122 static void ea3250_spi_cs_set(u32 control)
123 {
124         gpio_set_value(SPI0_CS_GPIO, (int) control);
125 }
126
127 /* Touch screen SPI parameters */
128 static struct pl022_config_chip spi0_chip_info = {
129         .lbm                    = LOOPBACK_DISABLED,
130         .com_mode               = INTERRUPT_TRANSFER,
131         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
132         .hierarchy              = SSP_MASTER,
133         .slave_tx_disable       = 0,
134         .endian_tx              = SSP_TX_LSB,
135         .endian_rx              = SSP_RX_LSB,
136         .data_size              = SSP_DATA_BITS_8,
137         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
138         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
139         .clk_phase              = SSP_CLK_FIRST_EDGE,
140         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
141         .ctrl_len               = SSP_BITS_8,
142         .wait_state             = SSP_MWIRE_WAIT_ZERO,
143         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
144         .cs_control             = ea3250_spi_cs_set,
145 };
146
147 /* Touch screen interrupt status function */
148 static int ea3250_ads7846_pendown_state(void)
149 {
150         u32 tmp = gpio_get_value(ADS_TS_GPIO);
151         return (tmp == 0);
152 }
153
154 /* Touch screen platform data */
155 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
156         .debounce_max   = 10,
157         .debounce_tol   = 3,
158         .pressure_max   = 1024,
159         .get_pendown_state = ea3250_ads7846_pendown_state,
160 };
161
162 /*
163  * SPI based LCDC data
164  */
165 /* LCDC chip select function */
166 static void ea3250_spi_lcdc_cs_set(u32 control)
167 {
168         gpio_set_value(LCD_CS_GPIO, (int) control);
169 }
170
171 /* LCDC SPI parameters */
172 static struct pl022_config_chip spi0_chip_info1 = {
173         .lbm                    = LOOPBACK_DISABLED,
174         .com_mode               = INTERRUPT_TRANSFER,
175         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
176         .hierarchy              = SSP_MASTER,
177         .slave_tx_disable       = 0,
178         .endian_tx              = SSP_TX_LSB,
179         .endian_rx              = SSP_RX_LSB,
180         .data_size              = SSP_DATA_BITS_8,
181         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
182         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
183         .clk_phase              = SSP_CLK_FIRST_EDGE,
184         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
185         .ctrl_len               = SSP_BITS_8,
186         .wait_state             = SSP_MWIRE_WAIT_ZERO,
187         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
188         .cs_control             = ea3250_spi_lcdc_cs_set,
189 };
190
191 /* SPI devices registration */
192 static int __init ea3250_spi_devices_register(void)
193 {
194 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
195         static struct spi_board_info info[] = {
196                 {
197                         .modalias = "spidev",
198                         .max_speed_hz = 2500000,
199                         .bus_num = 0,
200                         .chip_select = 0,
201                         .controller_data = &spi0_chip_info,
202                 },
203         };
204 #else
205         struct spi_board_info info[] = {
206                 {
207                         .modalias      = "ads7846",
208                         .max_speed_hz  = 2500000,
209                         .chip_select   = 0,
210                         .irq           = IRQ_LPC32XX_GPIO_00,
211                         .platform_data = &ea_ads7846_platform_data,
212                         .controller_data = &spi0_chip_info,
213                 },
214                 {
215                         .modalias      = "ea3250_lcdc",
216                         .max_speed_hz  = 10000000,
217                         .chip_select   = 1,
218                         .controller_data = &spi0_chip_info1,
219                 },
220         };
221 #endif
222
223         /* Configure ADS TS INT GPIO pin as input */
224         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
225                 return -EIO;
226         if(gpio_direction_input(ADS_TS_GPIO))
227                 return -EIO;
228
229         /* Configure LCDC CS GPIO pin */
230         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
231                 return -EIO;
232         if(gpio_direction_output(LCD_CS_GPIO, 1))
233                 return -EIO;
234
235         return spi_register_board_info(info, ARRAY_SIZE(info));
236 }
237 arch_initcall(ea3250_spi_devices_register);
238
239 #if defined (CONFIG_FB_ARMCLCD)
240 /*
241  * LCDC AMBA Driver Board Functions
242  */
243 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
244 /*
245  * Support for Embedded Artists 3.2 inch QVGA LCD panel
246  */
247 static struct clcd_panel conn_lcd_panel = {
248         .mode           = {
249                 .name           = "QVGA portrait",
250                 .refresh        = 60,
251                 .xres           = 240,
252                 .yres           = 320,
253                 .pixclock       = 121654,
254                 .left_margin    = 28,
255                 .right_margin   = 10,
256                 .upper_margin   = 2,
257                 .lower_margin   = 2,
258                 .hsync_len      = 3,
259                 .vsync_len      = 2,
260                 .sync           = 0,
261                 .vmode          = FB_VMODE_NONINTERLACED,
262         },
263         .width          = -1,
264         .height         = -1,
265         .tim2           = (TIM2_IVS | TIM2_IHS),
266         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
267                                 CNTL_LCDBPP16_565),
268         .bpp            = 16,
269 };
270
271 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
272 /*
273  * Support for Embedded Artists 2.8 inch QVGA OLED panel
274 */
275 static struct clcd_panel conn_lcd_panel = {
276         .mode           = {
277                 .name           = "QVGA portrait",
278                 .refresh        = 60,
279                 .xres           = 240,
280                 .yres           = 320,
281                 .pixclock       = 176366,
282                 .left_margin    = 33,
283                 .right_margin   = 26,
284                 .upper_margin   = 3,
285                 .lower_margin   = 8,
286                 .hsync_len      = 32,
287                 .vsync_len      = 4,
288                 .sync           = 0,
289                 .vmode          = FB_VMODE_NONINTERLACED,
290         },
291         .width          = -1,
292         .height         = -1,
293         .tim2           = (TIM2_IVS | TIM2_IHS),
294         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
295                                 CNTL_LCDBPP16_565),
296         .bpp            = 16,
297 };
298 #endif
299
300 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
301 {
302         dma_addr_t dma;
303
304         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
305                         PANEL_SIZE, &dma, GFP_KERNEL);
306         if (!fb->fb.screen_base) {
307                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
308                 return -ENOMEM;
309         }
310
311         fb->fb.fix.smem_start = dma;
312         fb->fb.fix.smem_len = PANEL_SIZE;
313         fb->panel = &conn_lcd_panel;
314
315         if (gpio_request(SSEL0_GPIO5, "Unused GPIO5 input"))
316                 return -EIO;
317         if(gpio_direction_input(SSEL0_GPIO5))
318                 return -EIO;
319
320         /* Configure LCDC RS GPIO pin */
321         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
322                 return -EIO;
323
324         if(gpio_direction_output(LCD_RS_GPIO, 1))
325                 return -EIO;
326
327         /* Configure LCDC Backlight GPIO pin */
328         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
329                 return -EIO;
330
331 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
332         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
333 #else
334         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
335 #endif
336                 return -EIO;
337         }
338
339         return 0;
340 }
341
342 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
343 {
344         return dma_mmap_writecombine(&fb->dev->dev, vma,
345                                      fb->fb.screen_base,
346                                      fb->fb.fix.smem_start,
347                                      fb->fb.fix.smem_len);
348 }
349
350 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
351 {
352         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
353                               fb->fb.screen_base, fb->fb.fix.smem_start);
354 }
355
356 static void spiSend(u8 *buf, size_t len)
357 {
358         BUG_ON(ea3250_spi_lcd_dev == NULL);
359         spi_write(ea3250_spi_lcd_dev, buf, len);
360 }
361
362 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
363 static void writeToDisp(u16 data)
364 {
365         u8 buf[3];
366
367         /* Initiliase buffer */
368         buf[0] = 0x72;
369         buf[1] = data >> 8;
370         buf[2] = data & 0xff;
371         spiSend(buf, 3);
372 }
373 #endif
374
375 static void writeToReg(u16 addr, u16 data)
376 {
377         u8 buf[3];
378
379 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
380         RESET_RS;
381         buf[0] = 0x00;
382         buf[1] = addr & 0xff;
383         spiSend(buf, 2);
384
385         SET_RS;
386         buf[0] = data >> 8;
387         buf[1] = data & 0xff;
388         spiSend(buf, 2);
389
390         RESET_RS;
391         buf[0] = 0x00;
392         buf[1] = 0x22;
393         spiSend(buf, 2);
394 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
395         buf[0] = 0x70;
396         buf[1] = data >> 8;
397         buf[2] = data & 0xff;
398         spiSend(buf, 3);
399 #endif
400
401 }
402
403 static void clcd_display_init(void)
404 {
405         u32 tmp;
406
407         /* setup MUX register to use SSP0 */
408         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
409         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
410
411 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
412
413         writeToReg (0x00,0x0001);
414         mdelay(20);
415         writeToReg (0x03,0xA2A4);
416         writeToReg (0x0C,0x0004);
417         writeToReg (0x0D,0x0308);
418         writeToReg (0x0E,0x3000);
419         mdelay(50);
420         writeToReg (0x1E,0x00AF);
421         writeToReg (0x01,0x2B3F);
422         writeToReg (0x02,0x0600);
423         writeToReg (0x10,0x0000);
424         writeToReg (0x07,0x0233);
425         writeToReg (0x0B,0x0039);
426         writeToReg (0x0F,0x0000);
427         mdelay(50);
428
429         writeToReg (0x30,0x0707);
430         writeToReg (0x31,0x0204);
431         writeToReg (0x32,0x0204);
432         writeToReg (0x33,0x0502);
433         writeToReg (0x34,0x0507);
434         writeToReg (0x35,0x0204);
435         writeToReg (0x36,0x0204);
436         writeToReg (0x37,0x0502);
437         writeToReg (0x3A,0x0302);
438         writeToReg (0x3B,0x0302);
439
440         writeToReg (0x23,0x0000);
441         writeToReg (0x24,0x0000);
442
443         writeToReg (0x48,0x0000);
444         writeToReg (0x49,0x013F);
445         writeToReg (0x4A,0x0000);
446         writeToReg (0x4B,0x0000);
447
448         writeToReg (0x41,0x0000);
449         writeToReg (0x42,0x0000);
450
451         writeToReg (0x44,0xEF00);
452         writeToReg (0x45,0x0000);
453         writeToReg (0x46,0x013F);
454         mdelay(50);
455
456         writeToReg (0x44,0xEF00);
457         writeToReg (0x45,0x0000);
458         writeToReg (0x4E,0x0000);
459         writeToReg (0x4F,0x0000);
460         writeToReg (0x46,0x013F);
461
462 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
463
464         writeToReg(0,0x02);
465         writeToDisp(0x0192);
466
467         writeToReg(0,0x03);
468         writeToDisp(0x0130);
469
470         /* set standby off */
471         writeToReg(0,0x10);
472         writeToDisp(0x0000);
473
474         mdelay(100);
475
476         /* set display on */
477         writeToReg(0,0x05);
478         writeToDisp(0x0001);
479
480         /* enable image data transfer */
481         writeToReg(0,0x22);
482 #endif
483 }
484
485 void clcd_disable(struct clcd_fb *fb)
486 {
487         /* Disable the backlight */
488 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
489         gpio_set_value(BKL_POW_GPIO, 1);
490 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
491         gpio_set_value(BKL_POW_GPIO, 0);
492 #endif
493 }
494
495 void clcd_enable(struct clcd_fb *fb)
496 {
497         clcd_display_init();
498
499         /* Enable the backlight */
500 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
501         gpio_set_value(BKL_POW_GPIO, 0);
502 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
503         gpio_set_value(BKL_POW_GPIO, 1);
504 #endif
505
506 }
507
508 struct clcd_board lpc32xx_clcd_data = {
509 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
510         .name           = "Embedded Artists 3.2 inch LCD",
511 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
512         .name           = "Embedded Artists 2.8 inch OLED",
513 #else
514         .name           = "Unknown Display",
515 #endif
516         .check          = clcdfb_check,
517         .decode         = clcdfb_decode,
518         .disable        = clcd_disable,
519         .enable         = clcd_enable,
520         .setup          = lpc32xx_clcd_setup,
521         .mmap           = lpc32xx_clcd_mmap,
522         .remove         = lpc32xx_clcd_remove,
523 };
524
525 struct amba_device lpc32xx_clcd_device = {
526         .dev                            = {
527                 .coherent_dma_mask      = ~0,
528                 .init_name              = "dev:clcd",
529                 .platform_data          = &lpc32xx_clcd_data,
530         },
531         .res                            = {
532                 .start                  = LPC32XX_LCD_BASE,
533                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
534                 .flags                  = IORESOURCE_MEM,
535         },
536         .dma_mask                       = ~0,
537         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
538 };
539 #endif
540
541 /*
542  * SPI LCDC Driver Probe function
543  */
544 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
545 {
546         int err;
547
548         spi->mode = SPI_MODE_0;
549         ea3250_spi_lcd_dev = spi;
550
551         /* SPI settings */
552         err = spi_setup(spi);
553         if (err < 0) {
554                 dev_err(&spi->dev, "Err in setting SPI \n");
555                 return err;
556         }
557         return 0;
558 }
559
560 /*
561  *  * SPI LCDC Driver remove function
562  *   * */
563 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
564 {
565         return 0;
566 }
567
568 static struct spi_driver ea3250_spi_lcdc_driver = {
569         .driver = {
570                 .name   = "ea3250_lcdc",
571                 .bus    = &spi_bus_type,
572                 .owner  = THIS_MODULE,
573         },
574         .probe  = ea3250_spi_lcdc_probe,
575         .remove = __devexit_p(ea3250_spi_lcdc_remove),
576 };
577
578 void __init ea3250_spi_lcdc_drv_init(void)
579 {
580         spi_register_driver(&ea3250_spi_lcdc_driver);
581 }
582
583 /* AMBA based devices list */
584 static struct amba_device *amba_devs[] __initdata = {
585         &lpc32xx_ssp0_device,
586 #if defined (CONFIG_FB_ARMCLCD)
587         &lpc32xx_clcd_device,
588 #endif
589 };
590
591 /*
592  * Register AMBA BUS Devices.
593  * Call AMBA device restration after SPI driver probe(),
594  * as LCD controller uses SPI driver for initialization
595  */
596 static int __init ea3250_amba_devices_register(void)
597 {
598         u32 i = 0;
599
600         /* Add AMBA devices */
601         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
602                 struct amba_device *d = amba_devs[i];
603                 amba_device_register(d, &iomem_resource);
604         }
605         
606         return 0;
607 }
608 device_initcall_sync(ea3250_amba_devices_register);
609
610 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
611 /*
612  *  * Board specific NAND setup data
613  *   */
614 static int nandwp_enable(int enable)
615 {
616         if (enable != 0)
617                 gpio_set_value(NAND_WP_GPIO,0);
618         else
619                 gpio_set_value(NAND_WP_GPIO,1);
620
621         return 1;
622 }
623 #define BLK_SIZE (2048 * 64)
624 static struct mtd_partition __initdata ea3250_nand_partition[] = {
625         {
626                 .name   = "ea3250-boot",
627                 .offset = 0,
628                 .size   = (BLK_SIZE * 25)
629         },
630         {
631                 .name   = "ea3250-uboot",
632                 .offset = MTDPART_OFS_APPEND,
633                 .size   = (BLK_SIZE * 100)
634         },
635         {
636                 .name   = "ea3250-ubt-prms",
637                 .offset = MTDPART_OFS_APPEND,
638                 .size   = (BLK_SIZE * 2)
639         },
640         {
641                 .name   = "ea3250-kernel",
642                 .offset = MTDPART_OFS_APPEND,
643                 .size   = (BLK_SIZE * 32)
644         },
645         {
646                 .name   = "ea3250-jffs2",
647                 .offset = MTDPART_OFS_APPEND,
648                 .size   = MTDPART_SIZ_FULL
649         },
650 };
651 static struct mtd_partition * __init ea3250_nand_partitions(int size, int *num_partitions)
652 {
653         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
654         return ea3250_nand_partition;
655 }
656 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
657 {
658         .wdr_clks               = 14,
659         .wwidth                 = 260000000,
660         .whold                  = 104000000,
661         .wsetup                 = 200000000,
662         .rdr_clks               = 14,
663         .rwidth                 = 34666666,
664         .rhold                  = 104000000,
665         .rsetup                 = 200000000,
666         .use16bus               = 0,
667         .enable_write_prot      = nandwp_enable,
668         .partition_info         = ea3250_nand_partitions,
669 };
670
671 /*
672  *  * SLC NAND resources
673  *   */
674 static struct resource slc_nand_resources[] = {
675         [0] = {
676                 .start  = LPC32XX_SLC_BASE,
677                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
678                 .flags  = IORESOURCE_MEM,
679         },
680
681         [1] = {
682                 .start  = IRQ_LPC32XX_FLASH,
683                 .end    = IRQ_LPC32XX_FLASH,
684                 .flags  = IORESOURCE_IRQ,
685         },
686
687 };
688
689 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
690 static struct platform_device lpc32xx_slc_nand_device = {
691         .name           = "lpc32xx-nand",
692         .id             = 0,
693         .dev            = {
694                                 .platform_data  = &lpc32xx_nandcfg,
695                                 .dma_mask    = &lpc32xx_slc_dma_mask,
696                                 .coherent_dma_mask = ~0UL,
697
698         },
699         .num_resources  = ARRAY_SIZE(slc_nand_resources),
700         .resource       = slc_nand_resources,
701 };
702 #endif
703
704 /*
705  * Network Support
706  */
707 static struct lpc_net_cfg lpc32xx_netdata =
708 {
709         .phy_irq        = -1,
710         .phy_mask       = 0xFFFFFFF0,
711 };
712
713 static struct resource net_resources[] = {
714         [0] = {
715                 .start  = LPC32XX_ETHERNET_BASE,
716                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
717                 .flags  = IORESOURCE_MEM,
718         },
719
720         [1] = {
721                 .start  = IRQ_LPC32XX_ETHERNET,
722                 .end    = IRQ_LPC32XX_ETHERNET,
723                 .flags  = IORESOURCE_IRQ,
724         },
725
726 };
727
728 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
729 static struct platform_device lpc32xx_net_device = {
730         .name           = "lpc-net",
731         .id             = 0,
732         .dev            = {
733                 .dma_mask = &lpc32xx_mac_dma_mask,
734                 .coherent_dma_mask = 0xffffffffUL,
735                 .platform_data  = &lpc32xx_netdata,
736         },
737         .num_resources  = ARRAY_SIZE(net_resources),
738         .resource       = net_resources,
739 };
740
741 /*
742  * I2C devices support
743  */
744 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
745         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
746 #if defined (CONFIG_SENSORS_PCA9532)
747                 {
748                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
749
750                 },
751 #endif
752 #if defined (CONFIG_AT24)
753                 {
754                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
755                 },
756 #endif
757         };
758 #endif
759
760 static struct platform_device* ea3250_devs[] __initdata = {
761         &lpc32xx_i2c0_device,
762         &lpc32xx_i2c1_device,
763         &lpc32xx_i2c2_device,
764         &lpc32xx_watchdog_device,
765         &lpc32xx_gpio_led_device,
766         &lpc32xx_rtc_device,
767         &lpc32xx_net_device,
768 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
769         &lpc32xx_slc_nand_device,
770 #endif
771 #if defined(CONFIG_USB_OHCI_HCD)
772         &lpc32xx_ohci_device,
773 #endif
774 #if defined(CONFIG_USB_GADGET_LPC32XX)
775         &lpc32xx_usbd_device,
776 #endif
777 };
778
779 extern void __init ea3250_spi_lcdc_drv_init(void);
780
781 /*
782  * Board specific functions
783  */
784 void __init ea3250_board_init(void)
785 {
786         u32 tmp;
787
788         /* Intiliase GPIO */
789         lpc32xx_gpio_init();
790
791         /* Set SPI CS GPIO to output */
792         gpio_request(SPI0_CS_GPIO, "spi0 cs");
793         gpio_direction_output(SPI0_CS_GPIO, 1);
794
795         /* Setup network interface for RMII mode */
796         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
797         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
798         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
799         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
800
801         /* Setup SLC NAND controller */
802         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
803                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
804
805         /* Setup LCD muxing to RGB565 */
806         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
807                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
808                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
809         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
810         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
811
812         /* Set up I2C pull levels */
813         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
814         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
815                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
816         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
817
818         /* Enable DMA for I2S1 channel */
819         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
820         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
821         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
822
823         /* Initalise Serial device */
824         lpc32xx_serial_init();
825
826         /*
827          * AMBA peripheral clocks need to be enabled prior to AMBA device
828          * detection or a data fault will occur, so enable the clocks
829          * here. However, we don't want to enable them if the peripheral
830          * isn't included in the image
831          */
832         /* Initialise SSP clock */
833         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
834         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
835                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
836
837         /* Initialise LCD clock */
838         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
839         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
840                         LPC32XX_CLKPWR_LCDCLK_CTRL);
841
842         /* Enable SD card clock so AMBA driver will work correctly. The
843            AMBA driver needs the clock before the SD card controller
844            driver initializes it. The clock will turn off once the driver
845            has been initialized. */
846         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
847         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
848                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
849         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
850
851         /* Disable UART5->USB transparent mode or USB won't work */
852         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
853         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
854         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
855
856         /* Add platform devcies */
857         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
858
859         /* Register SPI driver */
860         ea3250_spi_lcdc_drv_init();
861         
862         /* Test clock needed for UDA1380 initial init */
863         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
864                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
865                         LPC32XX_CLKPWR_TEST_CLK_SEL);
866
867 #if defined (CONFIG_SENSORS_PCA9532) || defined (CONFIG_AT24)
868         i2c_register_board_info(0, ea3250_i2c_board_info,
869                         ARRAY_SIZE(ea3250_i2c_board_info));
870 #endif
871 }
872
873 static int __init lpc32xx_display_uid(void)
874 {
875         u32 uid[4];
876
877         lpc32xx_get_uid(uid);
878
879         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
880                         uid[3], uid[2], uid[1], uid[0]);
881
882         return 1;
883 }
884 arch_initcall(lpc32xx_display_uid);
885
886 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
887         /* Maintainer: Embedded Artists */
888         .phys_io        = LPC32XX_UART5_BASE,
889         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
890         .boot_params    = 0x80000100,
891         .map_io         = lpc32xx_map_io,
892         .init_irq       = lpc32xx_init_irq,
893         .timer          = &lpc32xx_timer,
894         .init_machine   = ea3250_board_init,
895         MACHINE_END
896
897 /* For backwards compatibility with older bootloaders only */
898 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
899         /* Maintainer: Embedded Artists */
900         .phys_io        = LPC32XX_UART5_BASE,
901         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
902         .boot_params    = 0x80000100,
903         .map_io         = lpc32xx_map_io,
904         .init_irq       = lpc32xx_init_irq,
905         .timer          = &lpc32xx_timer,
906         .init_machine   = ea3250_board_init,
907         MACHINE_END