arm:lpc32xx:spi/pl022 Add spi->mode support AMBA SPI driver
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / ea3250.c
1 /*
2  * arch/arm/mach-lpc32xx/ea3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/leds-pca9532.h>
29 #include <linux/gpio.h>
30 #include <linux/input.h>
31 #include <linux/amba/bus.h>
32 #include <linux/amba/clcd.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/amba/mmci.h>
35 #include <mtd/mtd-abi.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40
41 #include <mach/hardware.h>
42 #include <mach/platform.h>
43 #include <mach/board.h>
44 #include "common.h"
45
46 #include <linux/spi/ads7846.h>
47
48 #define I2C_PCA9532_ADDR 0x60
49 #define I2C_24LC256_ADDR 0x50
50
51 /*
52  * Mapped GPIOLIB GPIOs
53  */
54 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
55 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
56 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
57 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
58 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
59 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
60 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
61 #define SSEL0_GPIO5     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
62 #define MMC_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
63
64 /*
65  * LCD controller functions
66  */
67 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
68 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
69 #define PANEL_SIZE      (3 * SZ_64K)
70
71 /* SPI LCDC device structure */
72 struct spi_device *ea3250_spi_lcd_dev = NULL;
73
74 /*
75  * Tick LED
76  */
77 static struct gpio_led phy_leds[] = {
78         {
79                 .name                   = "led0",
80                 .gpio                   = LED_GPIO,
81                 .active_low             = 1,
82                 .default_trigger        = "heartbeat",
83         },
84 };
85
86 static struct gpio_led_platform_data led_data = {
87         .leds = phy_leds,
88         .num_leds = ARRAY_SIZE(phy_leds),
89 };
90
91 static struct platform_device lpc32xx_gpio_led_device = {
92         .name                   = "leds-gpio",
93         .id                     = -1,
94         .dev.platform_data      = &led_data,
95 };
96
97 static struct pca9532_platform_data ea3250_leds = {
98         .leds = {
99         {       .type = PCA9532_TYPE_NONE }, /* Key 1 */
100         {       .type = PCA9532_TYPE_NONE }, /* Key 2 */
101         {       .type = PCA9532_TYPE_NONE }, /* Key 3 */
102         {       .type = PCA9532_TYPE_NONE }, /* Key 4 */
103         {       .type = PCA9532_TYPE_NONE }, /* MMC CD */
104         {       .type = PCA9532_TYPE_NONE }, /* MMC WP */
105         {       .type = PCA9532_TYPE_NONE }, /* not used */
106         {       .type = PCA9532_TYPE_NONE }, /* not used */
107         {       .name = "eabb:red:led1",
108                 .state = PCA9532_OFF,
109                 .type = PCA9532_TYPE_LED,
110         },
111         {       .name = "eabb:red:led2",
112                 .state = PCA9532_OFF,
113                 .type = PCA9532_TYPE_LED,
114         },
115         {       .name = "eabb:red:led3",
116                 .state = PCA9532_OFF,
117                 .type = PCA9532_TYPE_LED,
118         },
119         {       .name = "eabb:red:led4",
120                 .state = PCA9532_OFF,
121                 .type = PCA9532_TYPE_LED,
122         },
123         {       .name = "eabb:red:led5",
124                 .state = PCA9532_OFF,
125                 .type = PCA9532_TYPE_LED,
126         },
127         {       .name = "eabb:red:led6",
128                 .state = PCA9532_OFF,
129                 .type = PCA9532_TYPE_LED,
130         },
131         {       .name = "eabb:red:led7",
132                 .state = PCA9532_OFF,
133                 .type = PCA9532_TYPE_LED,
134         },
135         {       .name = "eabb:red:led8",
136                 .state = PCA9532_OFF,
137                 .type = PCA9532_TYPE_LED,
138         }, },
139         .psc = { 0, 0 },
140         .pwm = { 0, 0 },
141 };
142
143 /*
144  * AMBA SSP (SPI)
145  */
146 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
147         .bus_id                 = 0,
148         .num_chipselect         = 2,
149         .enable_dma             = 0,
150 };
151
152 static struct amba_device lpc32xx_ssp0_device = {
153         .dev    = {
154                 .coherent_dma_mask      = ~0,
155                 .init_name              = "dev:ssp0",
156                 .platform_data          = &lpc32xx_ssp0_data,
157         },
158         .res                            = {
159                 .start                  = LPC32XX_SSP0_BASE,
160                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
161                 .flags                  = IORESOURCE_MEM,
162         },
163         .dma_mask                       = ~0,
164         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
165 };
166
167 /*
168  * Touchscreen device
169  */
170 /* Touch screen chip select function */
171 static void ea3250_spi_cs_set(u32 control)
172 {
173         gpio_set_value(SPI0_CS_GPIO, (int) control);
174 }
175
176 /* Touch screen SPI parameters */
177 static struct pl022_config_chip spi0_chip_info = {
178         .com_mode               = INTERRUPT_TRANSFER,
179         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
180         .hierarchy              = SSP_MASTER,
181         .slave_tx_disable       = 0,
182         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
183         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
184         .ctrl_len               = SSP_BITS_8,
185         .wait_state             = SSP_MWIRE_WAIT_ZERO,
186         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
187         .cs_control             = ea3250_spi_cs_set,
188 };
189
190 /* Touch screen interrupt status function */
191 static int ea3250_ads7846_pendown_state(void)
192 {
193         u32 tmp = gpio_get_value(ADS_TS_GPIO);
194         return (tmp == 0);
195 }
196
197 /* Touch screen platform data */
198 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
199         .debounce_max   = 10,
200         .debounce_tol   = 3,
201         .pressure_max   = 1024,
202         .get_pendown_state = ea3250_ads7846_pendown_state,
203         .wakeup = true,
204 };
205
206 /*
207  * SPI based LCDC data
208  */
209 /* LCDC chip select function */
210 static void ea3250_spi_lcdc_cs_set(u32 control)
211 {
212         gpio_set_value(LCD_CS_GPIO, (int) control);
213 }
214
215 /* LCDC SPI parameters */
216 static struct pl022_config_chip spi0_chip_info1 = {
217         .com_mode               = INTERRUPT_TRANSFER,
218         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
219         .hierarchy              = SSP_MASTER,
220         .slave_tx_disable       = 0,
221         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
222         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
223         .ctrl_len               = SSP_BITS_8,
224         .wait_state             = SSP_MWIRE_WAIT_ZERO,
225         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
226         .cs_control             = ea3250_spi_lcdc_cs_set,
227 };
228
229 /* SPI devices registration */
230 static int __init ea3250_spi_devices_register(void)
231 {
232 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
233         static struct spi_board_info info[] = {
234                 {
235                         .modalias = "spidev",
236                         .max_speed_hz = 2500000,
237                         .bus_num = 0,
238                         .chip_select = 0,
239                         .controller_data = &spi0_chip_info,
240                 },
241         };
242 #else
243         struct spi_board_info info[] = {
244                 {
245                         .modalias      = "ads7846",
246                         .max_speed_hz  = 2500000,
247                         .chip_select   = 0,
248                         .mode = SPI_MODE_0,
249                         .irq           = IRQ_LPC32XX_GPIO_00,
250                         .platform_data = &ea_ads7846_platform_data,
251                         .controller_data = &spi0_chip_info,
252                 },
253                 {
254                         .modalias      = "ea3250_lcdc",
255                         .max_speed_hz  = 10000000,
256                         .chip_select   = 1,
257                         .mode = SPI_MODE_0,
258                         .controller_data = &spi0_chip_info1,
259                 },
260         };
261 #endif
262
263         /* Configure ADS TS INT GPIO pin as input */
264         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
265                 return -EIO;
266         if(gpio_direction_input(ADS_TS_GPIO))
267                 return -EIO;
268
269         /* Configure LCDC CS GPIO pin */
270         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
271                 return -EIO;
272         if(gpio_direction_output(LCD_CS_GPIO, 1))
273                 return -EIO;
274
275         return spi_register_board_info(info, ARRAY_SIZE(info));
276 }
277 arch_initcall(ea3250_spi_devices_register);
278
279 #if defined (CONFIG_FB_ARMCLCD)
280 /*
281  * LCDC AMBA Driver Board Functions
282  */
283 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
284 /*
285  * Support for Embedded Artists 3.2 inch QVGA LCD panel
286  */
287 static struct clcd_panel conn_lcd_panel = {
288         .mode           = {
289                 .name           = "QVGA portrait",
290                 .refresh        = 60,
291                 .xres           = 240,
292                 .yres           = 320,
293                 .pixclock       = 121654,
294                 .left_margin    = 28,
295                 .right_margin   = 10,
296                 .upper_margin   = 2,
297                 .lower_margin   = 2,
298                 .hsync_len      = 3,
299                 .vsync_len      = 2,
300                 .sync           = 0,
301                 .vmode          = FB_VMODE_NONINTERLACED,
302         },
303         .width          = -1,
304         .height         = -1,
305         .tim2           = (TIM2_IVS | TIM2_IHS),
306         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
307                                 CNTL_LCDBPP16_565),
308         .bpp            = 16,
309 };
310
311 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
312 /*
313  * Support for Embedded Artists 2.8 inch QVGA OLED panel
314 */
315 static struct clcd_panel conn_lcd_panel = {
316         .mode           = {
317                 .name           = "QVGA portrait",
318                 .refresh        = 60,
319                 .xres           = 240,
320                 .yres           = 320,
321                 .pixclock       = 176366,
322                 .left_margin    = 33,
323                 .right_margin   = 26,
324                 .upper_margin   = 3,
325                 .lower_margin   = 8,
326                 .hsync_len      = 32,
327                 .vsync_len      = 4,
328                 .sync           = 0,
329                 .vmode          = FB_VMODE_NONINTERLACED,
330         },
331         .width          = -1,
332         .height         = -1,
333         .tim2           = (TIM2_IVS | TIM2_IHS),
334         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
335                                 CNTL_LCDBPP16_565),
336         .bpp            = 16,
337 };
338 #endif
339
340 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
341 {
342         dma_addr_t dma;
343
344         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
345                         PANEL_SIZE, &dma, GFP_KERNEL);
346         if (!fb->fb.screen_base) {
347                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
348                 return -ENOMEM;
349         }
350
351         fb->fb.fix.smem_start = dma;
352         fb->fb.fix.smem_len = PANEL_SIZE;
353         fb->panel = &conn_lcd_panel;
354
355         if (gpio_request(SSEL0_GPIO5, "Unused GPIO5 input"))
356                 return -EIO;
357         if(gpio_direction_input(SSEL0_GPIO5))
358                 return -EIO;
359
360         /* Configure LCDC RS GPIO pin */
361         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
362                 return -EIO;
363
364         if(gpio_direction_output(LCD_RS_GPIO, 1))
365                 return -EIO;
366
367         /* Configure LCDC Backlight GPIO pin */
368         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
369                 return -EIO;
370
371 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
372         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
373 #else
374         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
375 #endif
376                 return -EIO;
377         }
378
379         return 0;
380 }
381
382 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
383 {
384         return dma_mmap_writecombine(&fb->dev->dev, vma,
385                                      fb->fb.screen_base,
386                                      fb->fb.fix.smem_start,
387                                      fb->fb.fix.smem_len);
388 }
389
390 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
391 {
392         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
393                               fb->fb.screen_base, fb->fb.fix.smem_start);
394 }
395
396 static void spiSend(u8 *buf, size_t len)
397 {
398         BUG_ON(ea3250_spi_lcd_dev == NULL);
399         spi_write(ea3250_spi_lcd_dev, buf, len);
400 }
401
402 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
403 static void writeToDisp(u16 data)
404 {
405         u8 buf[3];
406
407         /* Initiliase buffer */
408         buf[0] = 0x72;
409         buf[1] = data >> 8;
410         buf[2] = data & 0xff;
411         spiSend(buf, 3);
412 }
413 #endif
414
415 static void writeToReg(u16 addr, u16 data)
416 {
417         u8 buf[3];
418
419 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
420         RESET_RS;
421         buf[0] = 0x00;
422         buf[1] = addr & 0xff;
423         spiSend(buf, 2);
424
425         SET_RS;
426         buf[0] = data >> 8;
427         buf[1] = data & 0xff;
428         spiSend(buf, 2);
429
430         RESET_RS;
431         buf[0] = 0x00;
432         buf[1] = 0x22;
433         spiSend(buf, 2);
434 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
435         buf[0] = 0x70;
436         buf[1] = data >> 8;
437         buf[2] = data & 0xff;
438         spiSend(buf, 3);
439 #endif
440
441 }
442
443 static void clcd_display_init(void)
444 {
445         u32 tmp;
446
447         /* setup MUX register to use SSP0 */
448         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
449         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
450
451 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
452
453         writeToReg (0x00,0x0001);
454         mdelay(20);
455         writeToReg (0x03,0xA2A4);
456         writeToReg (0x0C,0x0004);
457         writeToReg (0x0D,0x0308);
458         writeToReg (0x0E,0x3000);
459         mdelay(50);
460         writeToReg (0x1E,0x00AF);
461         writeToReg (0x01,0x2B3F);
462         writeToReg (0x02,0x0600);
463         writeToReg (0x10,0x0000);
464         writeToReg (0x07,0x0233);
465         writeToReg (0x0B,0x0039);
466         writeToReg (0x0F,0x0000);
467         mdelay(50);
468
469         writeToReg (0x30,0x0707);
470         writeToReg (0x31,0x0204);
471         writeToReg (0x32,0x0204);
472         writeToReg (0x33,0x0502);
473         writeToReg (0x34,0x0507);
474         writeToReg (0x35,0x0204);
475         writeToReg (0x36,0x0204);
476         writeToReg (0x37,0x0502);
477         writeToReg (0x3A,0x0302);
478         writeToReg (0x3B,0x0302);
479
480         writeToReg (0x23,0x0000);
481         writeToReg (0x24,0x0000);
482
483         writeToReg (0x48,0x0000);
484         writeToReg (0x49,0x013F);
485         writeToReg (0x4A,0x0000);
486         writeToReg (0x4B,0x0000);
487
488         writeToReg (0x41,0x0000);
489         writeToReg (0x42,0x0000);
490
491         writeToReg (0x44,0xEF00);
492         writeToReg (0x45,0x0000);
493         writeToReg (0x46,0x013F);
494         mdelay(50);
495
496         writeToReg (0x44,0xEF00);
497         writeToReg (0x45,0x0000);
498         writeToReg (0x4E,0x0000);
499         writeToReg (0x4F,0x0000);
500         writeToReg (0x46,0x013F);
501
502 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
503
504         writeToReg(0,0x02);
505         writeToDisp(0x0192);
506
507         writeToReg(0,0x03);
508         writeToDisp(0x0130);
509
510         /* set standby off */
511         writeToReg(0,0x10);
512         writeToDisp(0x0000);
513
514         mdelay(100);
515
516         /* set display on */
517         writeToReg(0,0x05);
518         writeToDisp(0x0001);
519
520         /* enable image data transfer */
521         writeToReg(0,0x22);
522 #endif
523 }
524
525 void clcd_disable(struct clcd_fb *fb)
526 {
527         /* Disable the backlight */
528 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
529         gpio_set_value(BKL_POW_GPIO, 1);
530 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
531         gpio_set_value(BKL_POW_GPIO, 0);
532 #endif
533 }
534
535 void clcd_enable(struct clcd_fb *fb)
536 {
537         clcd_display_init();
538
539         /* Enable the backlight */
540 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
541         gpio_set_value(BKL_POW_GPIO, 0);
542 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
543         gpio_set_value(BKL_POW_GPIO, 1);
544 #endif
545
546 }
547
548 struct clcd_board lpc32xx_clcd_data = {
549 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
550         .name           = "Embedded Artists 3.2 inch LCD",
551 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
552         .name           = "Embedded Artists 2.8 inch OLED",
553 #else
554         .name           = "Unknown Display",
555 #endif
556         .check          = clcdfb_check,
557         .decode         = clcdfb_decode,
558         .disable        = clcd_disable,
559         .enable         = clcd_enable,
560         .setup          = lpc32xx_clcd_setup,
561         .mmap           = lpc32xx_clcd_mmap,
562         .remove         = lpc32xx_clcd_remove,
563 };
564
565 struct amba_device lpc32xx_clcd_device = {
566         .dev                            = {
567                 .coherent_dma_mask      = ~0,
568                 .init_name              = "dev:clcd",
569                 .platform_data          = &lpc32xx_clcd_data,
570         },
571         .res                            = {
572                 .start                  = LPC32XX_LCD_BASE,
573                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
574                 .flags                  = IORESOURCE_MEM,
575         },
576         .dma_mask                       = ~0,
577         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
578 };
579 #endif
580
581 /*
582  * SPI LCDC Driver Probe function
583  */
584 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
585 {
586         int err;
587
588         spi->mode = SPI_MODE_0;
589         ea3250_spi_lcd_dev = spi;
590
591         /* SPI settings */
592         err = spi_setup(spi);
593         if (err < 0) {
594                 dev_err(&spi->dev, "Err in setting SPI \n");
595                 return err;
596         }
597         return 0;
598 }
599
600 /*
601  *  * SPI LCDC Driver remove function
602  *   * */
603 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
604 {
605         return 0;
606 }
607
608 static struct spi_driver ea3250_spi_lcdc_driver = {
609         .driver = {
610                 .name   = "ea3250_lcdc",
611                 .bus    = &spi_bus_type,
612                 .owner  = THIS_MODULE,
613         },
614         .probe  = ea3250_spi_lcdc_probe,
615         .remove = __devexit_p(ea3250_spi_lcdc_remove),
616 };
617
618 void __init ea3250_spi_lcdc_drv_init(void)
619 {
620         spi_register_driver(&ea3250_spi_lcdc_driver);
621 }
622
623 #if defined (CONFIG_MMC_ARMMMCI)
624
625 /*
626  * Returns !0 when card is removed, 0 when present
627  */
628 unsigned int mmc_card_detect(struct device *dev)
629 {
630         /*
631          * This function may be adapted to retrieve the actual 'card detect'
632          * status over the I2C bus, from PCA9532 pin 8 (LED4). For now, simply
633          * indicate that a card is always present.
634         */
635         return 0;
636 }
637
638 /*
639  * Enable or disable SD slot power
640  */
641 void mmc_power_enable(int enable)
642 {
643         if (enable != 0)
644         {
645                 /* active low */
646                 gpio_set_value(MMC_POWER_GPIO,0);
647         }
648         else
649         {
650                 gpio_set_value(MMC_POWER_GPIO,0);
651         }
652 }
653
654 /*
655  * Board specific MMC driver data
656  */
657 struct mmci_platform_data lpc32xx_plat_data = {
658         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
659         .translate_vdd  = NULL,
660         .capabilities   = MMC_CAP_4_BIT_DATA,
661         /*
662          * Indicate no direct GPIO, so MMC driver will assume card is NOT
663          * write-protected
664          */
665         .gpio_wp        = -ENOSYS,
666         /*
667          * Indicate no direct GPIO, so MMC driver will call 'status' callback
668          * function
669          */
670         .gpio_cd        = -ENOSYS,
671         /*
672          * Callback function, used by MMC driver in case 'gpio_cd'
673          * equals -ENOSYS
674          */
675         .status         = mmc_card_detect,
676 };
677
678 /*
679  * SD card controller resources
680  */
681 struct amba_device lpc32xx_mmc_device = {
682         .dev                            = {
683                 .coherent_dma_mask      = ~0,
684                 .init_name              = "dev:mmc0",
685                 .platform_data          = &lpc32xx_plat_data,
686         },
687         .res                            = {
688                 .start                  = LPC32XX_SD_BASE,
689                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
690                 .flags                  = IORESOURCE_MEM,
691         },
692         .dma_mask                       = ~0,
693         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
694 };
695 #endif
696
697 /* AMBA based devices list */
698 static struct amba_device *amba_devs[] __initdata = {
699         &lpc32xx_ssp0_device,
700 #if defined (CONFIG_FB_ARMCLCD)
701         &lpc32xx_clcd_device,
702 #endif
703 #if defined (CONFIG_MMC_ARMMMCI)
704         &lpc32xx_mmc_device,
705 #endif
706 };
707
708 /*
709  * Register AMBA BUS Devices.
710  * Call AMBA device restration after SPI driver probe(),
711  * as LCD controller uses SPI driver for initialization
712  */
713 static int __init ea3250_amba_devices_register(void)
714 {
715         u32 i = 0;
716
717         /* Add AMBA devices */
718         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
719                 struct amba_device *d = amba_devs[i];
720                 amba_device_register(d, &iomem_resource);
721         }
722
723         return 0;
724 }
725 device_initcall_sync(ea3250_amba_devices_register);
726
727 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
728 /*
729  *  * Board specific NAND setup data
730  *   */
731 static int nandwp_enable(int enable)
732 {
733         if (enable != 0)
734                 gpio_set_value(NAND_WP_GPIO,0);
735         else
736                 gpio_set_value(NAND_WP_GPIO,1);
737
738         return 1;
739 }
740 #define BLK_SIZE (2048 * 64)
741 static struct mtd_partition ea3250_nand_partition[] = {
742         {
743                 .name   = "ea3250-boot",
744                 .offset = 0,
745                 .size   = (BLK_SIZE * 4),
746                 .mask_flags   = MTD_WRITEABLE,
747         },
748         {
749                 .name   = "ea3250-uboot",
750                 .offset = MTDPART_OFS_APPEND,
751                 .size   = (BLK_SIZE * 6)
752         },
753         {
754                 .name   = "ea3250-kernel",
755                 .offset = MTDPART_OFS_APPEND,
756                 .size   = (BLK_SIZE * 32)
757         },
758         {
759                 .name   = "ea3250-jffs2",
760                 .offset = MTDPART_OFS_APPEND,
761                 .size   = MTDPART_SIZ_FULL
762         },
763 };
764 static struct mtd_partition * ea3250_nand_partitions(int size, int *num_partitions)
765 {
766         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
767         return ea3250_nand_partition;
768 }
769 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
770 {
771         .wdr_clks               = 14,
772         .wwidth                 = 260000000,
773         .whold                  = 104000000,
774         .wsetup                 = 200000000,
775         .rdr_clks               = 14,
776         .rwidth                 = 34666666,
777         .rhold                  = 104000000,
778         .rsetup                 = 200000000,
779         .use_bbt                = true,
780         .polled_completion      = false,
781         .enable_write_prot      = nandwp_enable,
782         .partition_info         = ea3250_nand_partitions,
783 };
784
785 /*
786  *  * SLC NAND resources
787  *   */
788 static struct resource slc_nand_resources[] = {
789         [0] = {
790                 .start  = LPC32XX_SLC_BASE,
791                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
792                 .flags  = IORESOURCE_MEM,
793         },
794
795         [1] = {
796                 .start  = IRQ_LPC32XX_FLASH,
797                 .end    = IRQ_LPC32XX_FLASH,
798                 .flags  = IORESOURCE_IRQ,
799         },
800
801 };
802
803 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
804 static struct platform_device lpc32xx_slc_nand_device = {
805         .name           = "lpc32xx-nand",
806         .id             = 0,
807         .dev            = {
808                                 .platform_data  = &lpc32xx_nandcfg,
809                                 .dma_mask    = &lpc32xx_slc_dma_mask,
810                                 .coherent_dma_mask = ~0UL,
811
812         },
813         .num_resources  = ARRAY_SIZE(slc_nand_resources),
814         .resource       = slc_nand_resources,
815 };
816 #endif
817
818 /*
819  * Network Support
820  */
821 static struct lpc_net_cfg lpc32xx_netdata =
822 {
823         .phy_irq        = -1,
824         .phy_mask       = 0xFFFFFFF0,
825 };
826
827 static struct resource net_resources[] = {
828         [0] = {
829                 .start  = LPC32XX_ETHERNET_BASE,
830                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
831                 .flags  = IORESOURCE_MEM,
832         },
833
834         [1] = {
835                 .start  = IRQ_LPC32XX_ETHERNET,
836                 .end    = IRQ_LPC32XX_ETHERNET,
837                 .flags  = IORESOURCE_IRQ,
838         },
839
840 };
841
842 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
843 static struct platform_device lpc32xx_net_device = {
844         .name           = "lpc-net",
845         .id             = 0,
846         .dev            = {
847                 .dma_mask = &lpc32xx_mac_dma_mask,
848                 .coherent_dma_mask = 0xffffffffUL,
849                 .platform_data  = &lpc32xx_netdata,
850         },
851         .num_resources  = ARRAY_SIZE(net_resources),
852         .resource       = net_resources,
853 };
854
855 /*
856  * I2C devices support
857  */
858 #if defined (CONFIG_LEDS_PCA9532) || defined (CONFIG_AT24)
859         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
860 #if defined (CONFIG_LEDS_PCA9532)
861                 {
862                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
863                         .platform_data = &ea3250_leds,
864                 },
865 #endif
866 #if defined (CONFIG_AT24)
867                 {
868                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
869                 },
870 #endif
871         };
872 #endif
873
874 static struct platform_device* ea3250_devs[] __initdata = {
875         &lpc32xx_i2c0_device,
876         &lpc32xx_i2c1_device,
877         &lpc32xx_i2c2_device,
878         &lpc32xx_watchdog_device,
879         &lpc32xx_gpio_led_device,
880         &lpc32xx_rtc_device,
881         &lpc32xx_net_device,
882 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
883         &lpc32xx_slc_nand_device,
884 #endif
885 #if defined(CONFIG_USB_OHCI_HCD)
886         &lpc32xx_ohci_device,
887 #endif
888 #if defined(CONFIG_USB_GADGET_LPC32XX)
889         &lpc32xx_usbd_device,
890 #endif
891 };
892
893 extern void __init ea3250_spi_lcdc_drv_init(void);
894
895 /*
896  * Board specific functions
897  */
898 void __init ea3250_board_init(void)
899 {
900         u32 tmp;
901
902         /* Intiliase GPIO */
903         lpc32xx_gpio_init();
904
905 #if defined (CONFIG_MMC_ARMMMCI)
906         /* Enable SD slot power */
907         mmc_power_enable(1);
908 #endif
909
910         /* Set SPI CS GPIO to output */
911         gpio_request(SPI0_CS_GPIO, "spi0 cs");
912         gpio_direction_output(SPI0_CS_GPIO, 1);
913
914         /* Setup network interface for RMII mode */
915         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
916         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
917         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
918         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
919
920         /* Setup SLC NAND controller */
921         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
922                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
923
924         /* Setup LCD muxing to RGB565 */
925         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
926                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
927                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
928         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
929         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
930
931         /* Set up I2C pull levels */
932         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
933         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
934                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
935         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
936
937         /* Enable DMA for I2S1 channel */
938         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
939         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
940         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
941
942         /* Initalise Serial device */
943         lpc32xx_serial_init();
944
945         /*
946          * AMBA peripheral clocks need to be enabled prior to AMBA device
947          * detection or a data fault will occur, so enable the clocks
948          * here. However, we don't want to enable them if the peripheral
949          * isn't included in the image
950          */
951         /* Initialise SSP clock */
952         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
953         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
954                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
955
956         /* Initialise LCD clock */
957         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
958         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
959                         LPC32XX_CLKPWR_LCDCLK_CTRL);
960
961         /* Enable SD card clock so AMBA driver will work correctly. The
962            AMBA driver needs the clock before the SD card controller
963            driver initializes it. The clock will turn off once the driver
964            has been initialized. */
965         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
966         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
967                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
968         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
969
970         /* Disable UART5->USB transparent mode or USB won't work */
971         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
972         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
973         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
974
975         /* Add platform devcies */
976         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
977
978         /* Register SPI driver */
979         ea3250_spi_lcdc_drv_init();
980
981         /* Test clock needed for UDA1380 initial init */
982         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
983                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
984                         LPC32XX_CLKPWR_TEST_CLK_SEL);
985
986 #if defined (CONFIG_LEDS_PCA9532) || defined (CONFIG_AT24)
987         i2c_register_board_info(0, ea3250_i2c_board_info,
988                         ARRAY_SIZE(ea3250_i2c_board_info));
989 #endif
990 }
991
992 static int __init lpc32xx_display_uid(void)
993 {
994         u32 uid[4];
995
996         lpc32xx_get_uid(uid);
997
998         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
999                         uid[3], uid[2], uid[1], uid[0]);
1000
1001         return 1;
1002 }
1003 arch_initcall(lpc32xx_display_uid);
1004
1005 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
1006         /* Maintainer: Embedded Artists */
1007         .phys_io        = LPC32XX_UART5_BASE,
1008         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
1009         .boot_params    = 0x80000100,
1010         .map_io         = lpc32xx_map_io,
1011         .init_irq       = lpc32xx_init_irq,
1012         .timer          = &lpc32xx_timer,
1013         .init_machine   = ea3250_board_init,
1014         MACHINE_END
1015
1016 /* For backwards compatibility with older bootloaders only */
1017 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
1018         /* Maintainer: Embedded Artists */
1019         .phys_io        = LPC32XX_UART5_BASE,
1020         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
1021         .boot_params    = 0x80000100,
1022         .map_io         = lpc32xx_map_io,
1023         .init_irq       = lpc32xx_init_irq,
1024         .timer          = &lpc32xx_timer,
1025         .init_machine   = ea3250_board_init,
1026         MACHINE_END