ARM: LPC32xx: Add support for LED control via PCA9532
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / ea3250.c
1 /*
2  * arch/arm/mach-lpc32xx/ea3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/leds-pca9532.h>
29 #include <linux/gpio.h>
30 #include <linux/input.h>
31 #include <linux/amba/bus.h>
32 #include <linux/amba/clcd.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/amba/mmci.h>
35 #include <mtd/mtd-abi.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40
41 #include <mach/hardware.h>
42 #include <mach/platform.h>
43 #include <mach/board.h>
44 #include "common.h"
45
46 #include <linux/spi/ads7846.h>
47
48 #define I2C_PCA9532_ADDR 0x60
49 #define I2C_24LC256_ADDR 0x50
50
51 /*
52  * Mapped GPIOLIB GPIOs
53  */
54 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
55 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
56 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
57 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
58 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
59 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
60 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
61 #define SSEL0_GPIO5     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
62 #define MMC_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
63
64 /*
65  * LCD controller functions
66  */
67 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
68 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
69 #define PANEL_SIZE      (3 * SZ_64K)
70
71 /* SPI LCDC device structure */
72 struct spi_device *ea3250_spi_lcd_dev = NULL;
73
74 /*
75  * Tick LED
76  */
77 static struct gpio_led phy_leds[] = {
78         {
79                 .name                   = "led0",
80                 .gpio                   = LED_GPIO,
81                 .active_low             = 1,
82                 .default_trigger        = "heartbeat",
83         },
84 };
85
86 static struct gpio_led_platform_data led_data = {
87         .leds = phy_leds,
88         .num_leds = ARRAY_SIZE(phy_leds),
89 };
90
91 static struct platform_device lpc32xx_gpio_led_device = {
92         .name                   = "leds-gpio",
93         .id                     = -1,
94         .dev.platform_data      = &led_data,
95 };
96
97 static struct pca9532_platform_data ea3250_leds = {
98         .leds = {
99         {       .type = PCA9532_TYPE_NONE }, /* Key 1 */
100         {       .type = PCA9532_TYPE_NONE }, /* Key 2 */
101         {       .type = PCA9532_TYPE_NONE }, /* Key 3 */
102         {       .type = PCA9532_TYPE_NONE }, /* Key 4 */
103         {       .type = PCA9532_TYPE_NONE }, /* MMC CD */
104         {       .type = PCA9532_TYPE_NONE }, /* MMC WP */
105         {       .type = PCA9532_TYPE_NONE }, /* not used */
106         {       .type = PCA9532_TYPE_NONE }, /* not used */
107         {       .name = "eabb:red:led1",
108                 .state = PCA9532_OFF,
109                 .type = PCA9532_TYPE_LED,
110         },
111         {       .name = "eabb:red:led2",
112                 .state = PCA9532_OFF,
113                 .type = PCA9532_TYPE_LED,
114         },
115         {       .name = "eabb:red:led3",
116                 .state = PCA9532_OFF,
117                 .type = PCA9532_TYPE_LED,
118         },
119         {       .name = "eabb:red:led4",
120                 .state = PCA9532_OFF,
121                 .type = PCA9532_TYPE_LED,
122         },
123         {       .name = "eabb:red:led5",
124                 .state = PCA9532_OFF,
125                 .type = PCA9532_TYPE_LED,
126         },
127         {       .name = "eabb:red:led6",
128                 .state = PCA9532_OFF,
129                 .type = PCA9532_TYPE_LED,
130         },
131         {       .name = "eabb:red:led7",
132                 .state = PCA9532_OFF,
133                 .type = PCA9532_TYPE_LED,
134         },
135         {       .name = "eabb:red:led8",
136                 .state = PCA9532_OFF,
137                 .type = PCA9532_TYPE_LED,
138         }, },
139         .psc = { 0, 0 },
140         .pwm = { 0, 0 },
141 };
142
143 /*
144  * AMBA SSP (SPI)
145  */
146 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
147         .bus_id                 = 0,
148         .num_chipselect         = 2,
149         .enable_dma             = 0,
150 };
151
152 static struct amba_device lpc32xx_ssp0_device = {
153         .dev    = {
154                 .coherent_dma_mask      = ~0,
155                 .init_name              = "dev:ssp0",
156                 .platform_data          = &lpc32xx_ssp0_data,
157         },
158         .res                            = {
159                 .start                  = LPC32XX_SSP0_BASE,
160                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
161                 .flags                  = IORESOURCE_MEM,
162         },
163         .dma_mask                       = ~0,
164         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
165 };
166
167 /*
168  * Touchscreen device
169  */
170 /* Touch screen chip select function */
171 static void ea3250_spi_cs_set(u32 control)
172 {
173         gpio_set_value(SPI0_CS_GPIO, (int) control);
174 }
175
176 /* Touch screen SPI parameters */
177 static struct pl022_config_chip spi0_chip_info = {
178         .lbm                    = LOOPBACK_DISABLED,
179         .com_mode               = INTERRUPT_TRANSFER,
180         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
181         .hierarchy              = SSP_MASTER,
182         .slave_tx_disable       = 0,
183         .endian_tx              = SSP_TX_LSB,
184         .endian_rx              = SSP_RX_LSB,
185         .data_size              = SSP_DATA_BITS_8,
186         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
187         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
188         .clk_phase              = SSP_CLK_FIRST_EDGE,
189         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
190         .ctrl_len               = SSP_BITS_8,
191         .wait_state             = SSP_MWIRE_WAIT_ZERO,
192         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
193         .cs_control             = ea3250_spi_cs_set,
194 };
195
196 /* Touch screen interrupt status function */
197 static int ea3250_ads7846_pendown_state(void)
198 {
199         u32 tmp = gpio_get_value(ADS_TS_GPIO);
200         return (tmp == 0);
201 }
202
203 /* Touch screen platform data */
204 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
205         .debounce_max   = 10,
206         .debounce_tol   = 3,
207         .pressure_max   = 1024,
208         .get_pendown_state = ea3250_ads7846_pendown_state,
209 };
210
211 /*
212  * SPI based LCDC data
213  */
214 /* LCDC chip select function */
215 static void ea3250_spi_lcdc_cs_set(u32 control)
216 {
217         gpio_set_value(LCD_CS_GPIO, (int) control);
218 }
219
220 /* LCDC SPI parameters */
221 static struct pl022_config_chip spi0_chip_info1 = {
222         .lbm                    = LOOPBACK_DISABLED,
223         .com_mode               = INTERRUPT_TRANSFER,
224         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
225         .hierarchy              = SSP_MASTER,
226         .slave_tx_disable       = 0,
227         .endian_tx              = SSP_TX_LSB,
228         .endian_rx              = SSP_RX_LSB,
229         .data_size              = SSP_DATA_BITS_8,
230         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
231         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
232         .clk_phase              = SSP_CLK_FIRST_EDGE,
233         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
234         .ctrl_len               = SSP_BITS_8,
235         .wait_state             = SSP_MWIRE_WAIT_ZERO,
236         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
237         .cs_control             = ea3250_spi_lcdc_cs_set,
238 };
239
240 /* SPI devices registration */
241 static int __init ea3250_spi_devices_register(void)
242 {
243 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
244         static struct spi_board_info info[] = {
245                 {
246                         .modalias = "spidev",
247                         .max_speed_hz = 2500000,
248                         .bus_num = 0,
249                         .chip_select = 0,
250                         .controller_data = &spi0_chip_info,
251                 },
252         };
253 #else
254         struct spi_board_info info[] = {
255                 {
256                         .modalias      = "ads7846",
257                         .max_speed_hz  = 2500000,
258                         .chip_select   = 0,
259                         .irq           = IRQ_LPC32XX_GPIO_00,
260                         .platform_data = &ea_ads7846_platform_data,
261                         .controller_data = &spi0_chip_info,
262                 },
263                 {
264                         .modalias      = "ea3250_lcdc",
265                         .max_speed_hz  = 10000000,
266                         .chip_select   = 1,
267                         .controller_data = &spi0_chip_info1,
268                 },
269         };
270 #endif
271
272         /* Configure ADS TS INT GPIO pin as input */
273         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
274                 return -EIO;
275         if(gpio_direction_input(ADS_TS_GPIO))
276                 return -EIO;
277
278         /* Configure LCDC CS GPIO pin */
279         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
280                 return -EIO;
281         if(gpio_direction_output(LCD_CS_GPIO, 1))
282                 return -EIO;
283
284         return spi_register_board_info(info, ARRAY_SIZE(info));
285 }
286 arch_initcall(ea3250_spi_devices_register);
287
288 #if defined (CONFIG_FB_ARMCLCD)
289 /*
290  * LCDC AMBA Driver Board Functions
291  */
292 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
293 /*
294  * Support for Embedded Artists 3.2 inch QVGA LCD panel
295  */
296 static struct clcd_panel conn_lcd_panel = {
297         .mode           = {
298                 .name           = "QVGA portrait",
299                 .refresh        = 60,
300                 .xres           = 240,
301                 .yres           = 320,
302                 .pixclock       = 121654,
303                 .left_margin    = 28,
304                 .right_margin   = 10,
305                 .upper_margin   = 2,
306                 .lower_margin   = 2,
307                 .hsync_len      = 3,
308                 .vsync_len      = 2,
309                 .sync           = 0,
310                 .vmode          = FB_VMODE_NONINTERLACED,
311         },
312         .width          = -1,
313         .height         = -1,
314         .tim2           = (TIM2_IVS | TIM2_IHS),
315         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
316                                 CNTL_LCDBPP16_565),
317         .bpp            = 16,
318 };
319
320 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
321 /*
322  * Support for Embedded Artists 2.8 inch QVGA OLED panel
323 */
324 static struct clcd_panel conn_lcd_panel = {
325         .mode           = {
326                 .name           = "QVGA portrait",
327                 .refresh        = 60,
328                 .xres           = 240,
329                 .yres           = 320,
330                 .pixclock       = 176366,
331                 .left_margin    = 33,
332                 .right_margin   = 26,
333                 .upper_margin   = 3,
334                 .lower_margin   = 8,
335                 .hsync_len      = 32,
336                 .vsync_len      = 4,
337                 .sync           = 0,
338                 .vmode          = FB_VMODE_NONINTERLACED,
339         },
340         .width          = -1,
341         .height         = -1,
342         .tim2           = (TIM2_IVS | TIM2_IHS),
343         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
344                                 CNTL_LCDBPP16_565),
345         .bpp            = 16,
346 };
347 #endif
348
349 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
350 {
351         dma_addr_t dma;
352
353         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
354                         PANEL_SIZE, &dma, GFP_KERNEL);
355         if (!fb->fb.screen_base) {
356                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
357                 return -ENOMEM;
358         }
359
360         fb->fb.fix.smem_start = dma;
361         fb->fb.fix.smem_len = PANEL_SIZE;
362         fb->panel = &conn_lcd_panel;
363
364         if (gpio_request(SSEL0_GPIO5, "Unused GPIO5 input"))
365                 return -EIO;
366         if(gpio_direction_input(SSEL0_GPIO5))
367                 return -EIO;
368
369         /* Configure LCDC RS GPIO pin */
370         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
371                 return -EIO;
372
373         if(gpio_direction_output(LCD_RS_GPIO, 1))
374                 return -EIO;
375
376         /* Configure LCDC Backlight GPIO pin */
377         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
378                 return -EIO;
379
380 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
381         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
382 #else
383         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
384 #endif
385                 return -EIO;
386         }
387
388         return 0;
389 }
390
391 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
392 {
393         return dma_mmap_writecombine(&fb->dev->dev, vma,
394                                      fb->fb.screen_base,
395                                      fb->fb.fix.smem_start,
396                                      fb->fb.fix.smem_len);
397 }
398
399 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
400 {
401         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
402                               fb->fb.screen_base, fb->fb.fix.smem_start);
403 }
404
405 static void spiSend(u8 *buf, size_t len)
406 {
407         BUG_ON(ea3250_spi_lcd_dev == NULL);
408         spi_write(ea3250_spi_lcd_dev, buf, len);
409 }
410
411 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
412 static void writeToDisp(u16 data)
413 {
414         u8 buf[3];
415
416         /* Initiliase buffer */
417         buf[0] = 0x72;
418         buf[1] = data >> 8;
419         buf[2] = data & 0xff;
420         spiSend(buf, 3);
421 }
422 #endif
423
424 static void writeToReg(u16 addr, u16 data)
425 {
426         u8 buf[3];
427
428 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
429         RESET_RS;
430         buf[0] = 0x00;
431         buf[1] = addr & 0xff;
432         spiSend(buf, 2);
433
434         SET_RS;
435         buf[0] = data >> 8;
436         buf[1] = data & 0xff;
437         spiSend(buf, 2);
438
439         RESET_RS;
440         buf[0] = 0x00;
441         buf[1] = 0x22;
442         spiSend(buf, 2);
443 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
444         buf[0] = 0x70;
445         buf[1] = data >> 8;
446         buf[2] = data & 0xff;
447         spiSend(buf, 3);
448 #endif
449
450 }
451
452 static void clcd_display_init(void)
453 {
454         u32 tmp;
455
456         /* setup MUX register to use SSP0 */
457         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
458         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
459
460 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
461
462         writeToReg (0x00,0x0001);
463         mdelay(20);
464         writeToReg (0x03,0xA2A4);
465         writeToReg (0x0C,0x0004);
466         writeToReg (0x0D,0x0308);
467         writeToReg (0x0E,0x3000);
468         mdelay(50);
469         writeToReg (0x1E,0x00AF);
470         writeToReg (0x01,0x2B3F);
471         writeToReg (0x02,0x0600);
472         writeToReg (0x10,0x0000);
473         writeToReg (0x07,0x0233);
474         writeToReg (0x0B,0x0039);
475         writeToReg (0x0F,0x0000);
476         mdelay(50);
477
478         writeToReg (0x30,0x0707);
479         writeToReg (0x31,0x0204);
480         writeToReg (0x32,0x0204);
481         writeToReg (0x33,0x0502);
482         writeToReg (0x34,0x0507);
483         writeToReg (0x35,0x0204);
484         writeToReg (0x36,0x0204);
485         writeToReg (0x37,0x0502);
486         writeToReg (0x3A,0x0302);
487         writeToReg (0x3B,0x0302);
488
489         writeToReg (0x23,0x0000);
490         writeToReg (0x24,0x0000);
491
492         writeToReg (0x48,0x0000);
493         writeToReg (0x49,0x013F);
494         writeToReg (0x4A,0x0000);
495         writeToReg (0x4B,0x0000);
496
497         writeToReg (0x41,0x0000);
498         writeToReg (0x42,0x0000);
499
500         writeToReg (0x44,0xEF00);
501         writeToReg (0x45,0x0000);
502         writeToReg (0x46,0x013F);
503         mdelay(50);
504
505         writeToReg (0x44,0xEF00);
506         writeToReg (0x45,0x0000);
507         writeToReg (0x4E,0x0000);
508         writeToReg (0x4F,0x0000);
509         writeToReg (0x46,0x013F);
510
511 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
512
513         writeToReg(0,0x02);
514         writeToDisp(0x0192);
515
516         writeToReg(0,0x03);
517         writeToDisp(0x0130);
518
519         /* set standby off */
520         writeToReg(0,0x10);
521         writeToDisp(0x0000);
522
523         mdelay(100);
524
525         /* set display on */
526         writeToReg(0,0x05);
527         writeToDisp(0x0001);
528
529         /* enable image data transfer */
530         writeToReg(0,0x22);
531 #endif
532 }
533
534 void clcd_disable(struct clcd_fb *fb)
535 {
536         /* Disable the backlight */
537 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
538         gpio_set_value(BKL_POW_GPIO, 1);
539 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
540         gpio_set_value(BKL_POW_GPIO, 0);
541 #endif
542 }
543
544 void clcd_enable(struct clcd_fb *fb)
545 {
546         clcd_display_init();
547
548         /* Enable the backlight */
549 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
550         gpio_set_value(BKL_POW_GPIO, 0);
551 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
552         gpio_set_value(BKL_POW_GPIO, 1);
553 #endif
554
555 }
556
557 struct clcd_board lpc32xx_clcd_data = {
558 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
559         .name           = "Embedded Artists 3.2 inch LCD",
560 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
561         .name           = "Embedded Artists 2.8 inch OLED",
562 #else
563         .name           = "Unknown Display",
564 #endif
565         .check          = clcdfb_check,
566         .decode         = clcdfb_decode,
567         .disable        = clcd_disable,
568         .enable         = clcd_enable,
569         .setup          = lpc32xx_clcd_setup,
570         .mmap           = lpc32xx_clcd_mmap,
571         .remove         = lpc32xx_clcd_remove,
572 };
573
574 struct amba_device lpc32xx_clcd_device = {
575         .dev                            = {
576                 .coherent_dma_mask      = ~0,
577                 .init_name              = "dev:clcd",
578                 .platform_data          = &lpc32xx_clcd_data,
579         },
580         .res                            = {
581                 .start                  = LPC32XX_LCD_BASE,
582                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
583                 .flags                  = IORESOURCE_MEM,
584         },
585         .dma_mask                       = ~0,
586         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
587 };
588 #endif
589
590 /*
591  * SPI LCDC Driver Probe function
592  */
593 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
594 {
595         int err;
596
597         spi->mode = SPI_MODE_0;
598         ea3250_spi_lcd_dev = spi;
599
600         /* SPI settings */
601         err = spi_setup(spi);
602         if (err < 0) {
603                 dev_err(&spi->dev, "Err in setting SPI \n");
604                 return err;
605         }
606         return 0;
607 }
608
609 /*
610  *  * SPI LCDC Driver remove function
611  *   * */
612 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
613 {
614         return 0;
615 }
616
617 static struct spi_driver ea3250_spi_lcdc_driver = {
618         .driver = {
619                 .name   = "ea3250_lcdc",
620                 .bus    = &spi_bus_type,
621                 .owner  = THIS_MODULE,
622         },
623         .probe  = ea3250_spi_lcdc_probe,
624         .remove = __devexit_p(ea3250_spi_lcdc_remove),
625 };
626
627 void __init ea3250_spi_lcdc_drv_init(void)
628 {
629         spi_register_driver(&ea3250_spi_lcdc_driver);
630 }
631
632 #if defined (CONFIG_MMC_ARMMMCI)
633
634 /*
635  * Returns !0 when card is removed, 0 when present
636  */
637 unsigned int mmc_card_detect(struct device *dev)
638 {
639         /*
640          * This function may be adapted to retrieve the actual 'card detect'
641          * status over the I2C bus, from PCA9532 pin 8 (LED4). For now, simply
642          * indicate that a card is always present.
643         */
644         return 0;
645 }
646
647 /*
648  * Enable or disable SD slot power
649  */
650 void mmc_power_enable(int enable)
651 {
652         if (enable != 0)
653         {
654                 /* active low */
655                 gpio_set_value(MMC_POWER_GPIO,0);
656         }
657         else
658         {
659                 gpio_set_value(MMC_POWER_GPIO,0);
660         }
661 }
662
663 /*
664  * Board specific MMC driver data
665  */
666 struct mmci_platform_data lpc32xx_plat_data = {
667         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
668         .translate_vdd  = NULL,
669         .capabilities   = MMC_CAP_4_BIT_DATA,
670         /*
671          * Indicate no direct GPIO, so MMC driver will assume card is NOT
672          * write-protected
673          */
674         .gpio_wp        = -ENOSYS,
675         /*
676          * Indicate no direct GPIO, so MMC driver will call 'status' callback
677          * function
678          */
679         .gpio_cd        = -ENOSYS,
680         /*
681          * Callback function, used by MMC driver in case 'gpio_cd'
682          * equals -ENOSYS
683          */
684         .status         = mmc_card_detect,
685 };
686
687 /*
688  * SD card controller resources
689  */
690 struct amba_device lpc32xx_mmc_device = {
691         .dev                            = {
692                 .coherent_dma_mask      = ~0,
693                 .init_name              = "dev:mmc0",
694                 .platform_data          = &lpc32xx_plat_data,
695         },
696         .res                            = {
697                 .start                  = LPC32XX_SD_BASE,
698                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
699                 .flags                  = IORESOURCE_MEM,
700         },
701         .dma_mask                       = ~0,
702         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
703 };
704 #endif
705
706 /* AMBA based devices list */
707 static struct amba_device *amba_devs[] __initdata = {
708         &lpc32xx_ssp0_device,
709 #if defined (CONFIG_FB_ARMCLCD)
710         &lpc32xx_clcd_device,
711 #endif
712 #if defined (CONFIG_MMC_ARMMMCI)
713         &lpc32xx_mmc_device,
714 #endif
715 };
716
717 /*
718  * Register AMBA BUS Devices.
719  * Call AMBA device restration after SPI driver probe(),
720  * as LCD controller uses SPI driver for initialization
721  */
722 static int __init ea3250_amba_devices_register(void)
723 {
724         u32 i = 0;
725
726         /* Add AMBA devices */
727         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
728                 struct amba_device *d = amba_devs[i];
729                 amba_device_register(d, &iomem_resource);
730         }
731
732         return 0;
733 }
734 device_initcall_sync(ea3250_amba_devices_register);
735
736 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
737 /*
738  *  * Board specific NAND setup data
739  *   */
740 static int nandwp_enable(int enable)
741 {
742         if (enable != 0)
743                 gpio_set_value(NAND_WP_GPIO,0);
744         else
745                 gpio_set_value(NAND_WP_GPIO,1);
746
747         return 1;
748 }
749 #define BLK_SIZE (2048 * 64)
750 static struct mtd_partition ea3250_nand_partition[] = {
751         {
752                 .name   = "ea3250-boot",
753                 .offset = 0,
754                 .size   = (BLK_SIZE * 4),
755                 .mask_flags   = MTD_WRITEABLE,
756         },
757         {
758                 .name   = "ea3250-uboot",
759                 .offset = MTDPART_OFS_APPEND,
760                 .size   = (BLK_SIZE * 6)
761         },
762         {
763                 .name   = "ea3250-kernel",
764                 .offset = MTDPART_OFS_APPEND,
765                 .size   = (BLK_SIZE * 32)
766         },
767         {
768                 .name   = "ea3250-jffs2",
769                 .offset = MTDPART_OFS_APPEND,
770                 .size   = MTDPART_SIZ_FULL
771         },
772 };
773 static struct mtd_partition * ea3250_nand_partitions(int size, int *num_partitions)
774 {
775         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
776         return ea3250_nand_partition;
777 }
778 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
779 {
780         .wdr_clks               = 14,
781         .wwidth                 = 260000000,
782         .whold                  = 104000000,
783         .wsetup                 = 200000000,
784         .rdr_clks               = 14,
785         .rwidth                 = 34666666,
786         .rhold                  = 104000000,
787         .rsetup                 = 200000000,
788         .use_bbt                = true,
789         .polled_completion      = false,
790         .enable_write_prot      = nandwp_enable,
791         .partition_info         = ea3250_nand_partitions,
792 };
793
794 /*
795  *  * SLC NAND resources
796  *   */
797 static struct resource slc_nand_resources[] = {
798         [0] = {
799                 .start  = LPC32XX_SLC_BASE,
800                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
801                 .flags  = IORESOURCE_MEM,
802         },
803
804         [1] = {
805                 .start  = IRQ_LPC32XX_FLASH,
806                 .end    = IRQ_LPC32XX_FLASH,
807                 .flags  = IORESOURCE_IRQ,
808         },
809
810 };
811
812 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
813 static struct platform_device lpc32xx_slc_nand_device = {
814         .name           = "lpc32xx-nand",
815         .id             = 0,
816         .dev            = {
817                                 .platform_data  = &lpc32xx_nandcfg,
818                                 .dma_mask    = &lpc32xx_slc_dma_mask,
819                                 .coherent_dma_mask = ~0UL,
820
821         },
822         .num_resources  = ARRAY_SIZE(slc_nand_resources),
823         .resource       = slc_nand_resources,
824 };
825 #endif
826
827 /*
828  * Network Support
829  */
830 static struct lpc_net_cfg lpc32xx_netdata =
831 {
832         .phy_irq        = -1,
833         .phy_mask       = 0xFFFFFFF0,
834 };
835
836 static struct resource net_resources[] = {
837         [0] = {
838                 .start  = LPC32XX_ETHERNET_BASE,
839                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
840                 .flags  = IORESOURCE_MEM,
841         },
842
843         [1] = {
844                 .start  = IRQ_LPC32XX_ETHERNET,
845                 .end    = IRQ_LPC32XX_ETHERNET,
846                 .flags  = IORESOURCE_IRQ,
847         },
848
849 };
850
851 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
852 static struct platform_device lpc32xx_net_device = {
853         .name           = "lpc-net",
854         .id             = 0,
855         .dev            = {
856                 .dma_mask = &lpc32xx_mac_dma_mask,
857                 .coherent_dma_mask = 0xffffffffUL,
858                 .platform_data  = &lpc32xx_netdata,
859         },
860         .num_resources  = ARRAY_SIZE(net_resources),
861         .resource       = net_resources,
862 };
863
864 /*
865  * I2C devices support
866  */
867 #if defined (CONFIG_LEDS_PCA9532) || defined (CONFIG_AT24)
868         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
869 #if defined (CONFIG_LEDS_PCA9532)
870                 {
871                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
872                         .platform_data = &ea3250_leds,
873                 },
874 #endif
875 #if defined (CONFIG_AT24)
876                 {
877                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
878                 },
879 #endif
880         };
881 #endif
882
883 static struct platform_device* ea3250_devs[] __initdata = {
884         &lpc32xx_i2c0_device,
885         &lpc32xx_i2c1_device,
886         &lpc32xx_i2c2_device,
887         &lpc32xx_watchdog_device,
888         &lpc32xx_gpio_led_device,
889         &lpc32xx_rtc_device,
890         &lpc32xx_net_device,
891 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
892         &lpc32xx_slc_nand_device,
893 #endif
894 #if defined(CONFIG_USB_OHCI_HCD)
895         &lpc32xx_ohci_device,
896 #endif
897 #if defined(CONFIG_USB_GADGET_LPC32XX)
898         &lpc32xx_usbd_device,
899 #endif
900 };
901
902 extern void __init ea3250_spi_lcdc_drv_init(void);
903
904 /*
905  * Board specific functions
906  */
907 void __init ea3250_board_init(void)
908 {
909         u32 tmp;
910
911         /* Intiliase GPIO */
912         lpc32xx_gpio_init();
913
914 #if defined (CONFIG_MMC_ARMMMCI)
915         /* Enable SD slot power */
916         mmc_power_enable(1);
917 #endif
918
919         /* Set SPI CS GPIO to output */
920         gpio_request(SPI0_CS_GPIO, "spi0 cs");
921         gpio_direction_output(SPI0_CS_GPIO, 1);
922
923         /* Setup network interface for RMII mode */
924         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
925         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
926         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
927         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
928
929         /* Setup SLC NAND controller */
930         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
931                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
932
933         /* Setup LCD muxing to RGB565 */
934         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
935                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
936                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
937         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
938         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
939
940         /* Set up I2C pull levels */
941         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
942         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
943                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
944         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
945
946         /* Enable DMA for I2S1 channel */
947         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
948         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
949         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
950
951         /* Initalise Serial device */
952         lpc32xx_serial_init();
953
954         /*
955          * AMBA peripheral clocks need to be enabled prior to AMBA device
956          * detection or a data fault will occur, so enable the clocks
957          * here. However, we don't want to enable them if the peripheral
958          * isn't included in the image
959          */
960         /* Initialise SSP clock */
961         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
962         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
963                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
964
965         /* Initialise LCD clock */
966         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
967         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
968                         LPC32XX_CLKPWR_LCDCLK_CTRL);
969
970         /* Enable SD card clock so AMBA driver will work correctly. The
971            AMBA driver needs the clock before the SD card controller
972            driver initializes it. The clock will turn off once the driver
973            has been initialized. */
974         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
975         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
976                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
977         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
978
979         /* Disable UART5->USB transparent mode or USB won't work */
980         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
981         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
982         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
983
984         /* Add platform devcies */
985         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
986
987         /* Register SPI driver */
988         ea3250_spi_lcdc_drv_init();
989
990         /* Test clock needed for UDA1380 initial init */
991         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
992                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
993                         LPC32XX_CLKPWR_TEST_CLK_SEL);
994
995 #if defined (CONFIG_LEDS_PCA9532) || defined (CONFIG_AT24)
996         i2c_register_board_info(0, ea3250_i2c_board_info,
997                         ARRAY_SIZE(ea3250_i2c_board_info));
998 #endif
999 }
1000
1001 static int __init lpc32xx_display_uid(void)
1002 {
1003         u32 uid[4];
1004
1005         lpc32xx_get_uid(uid);
1006
1007         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
1008                         uid[3], uid[2], uid[1], uid[0]);
1009
1010         return 1;
1011 }
1012 arch_initcall(lpc32xx_display_uid);
1013
1014 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
1015         /* Maintainer: Embedded Artists */
1016         .phys_io        = LPC32XX_UART5_BASE,
1017         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
1018         .boot_params    = 0x80000100,
1019         .map_io         = lpc32xx_map_io,
1020         .init_irq       = lpc32xx_init_irq,
1021         .timer          = &lpc32xx_timer,
1022         .init_machine   = ea3250_board_init,
1023         MACHINE_END
1024
1025 /* For backwards compatibility with older bootloaders only */
1026 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
1027         /* Maintainer: Embedded Artists */
1028         .phys_io        = LPC32XX_UART5_BASE,
1029         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
1030         .boot_params    = 0x80000100,
1031         .map_io         = lpc32xx_map_io,
1032         .init_irq       = lpc32xx_init_irq,
1033         .timer          = &lpc32xx_timer,
1034         .init_machine   = ea3250_board_init,
1035         MACHINE_END