arm: lpc32xx: Fix several system suspend related issues
[linux-2.6.34-lpc32xx.git] / arch / arm / mach-lpc32xx / ea3250.c
1 /*
2  * arch/arm/mach-lpc32xx/ea3250.c
3  *
4  * Copyright (C) 2010 NXP Semiconductors
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/eeprom.h>
27 #include <linux/leds.h>
28 #include <linux/leds-pca9532.h>
29 #include <linux/gpio.h>
30 #include <linux/input.h>
31 #include <linux/amba/bus.h>
32 #include <linux/amba/clcd.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/amba/mmci.h>
35 #include <mtd/mtd-abi.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40
41 #include <mach/hardware.h>
42 #include <mach/platform.h>
43 #include <mach/board.h>
44 #include "common.h"
45
46 #include <linux/spi/ads7846.h>
47
48 #define I2C_PCA9532_ADDR 0x60
49 #define I2C_24LC256_ADDR 0x50
50
51 /*
52  * Mapped GPIOLIB GPIOs
53  */
54 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPIO_P2_GRP, 1)
55 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 11)
56 #define ADS_TS_GPIO     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
57 #define NAND_WP_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 19)
58 #define LCD_CS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
59 #define LCD_RS_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
60 #define BKL_POW_GPIO    LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 14)
61 #define SSEL0_GPIO5     LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
62 #define MMC_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
63
64 /*
65  * LCD controller functions
66  */
67 #define SET_RS          (gpio_set_value(LCD_RS_GPIO, 1))
68 #define RESET_RS        (gpio_set_value(LCD_RS_GPIO, 0))
69 #define PANEL_SIZE      (3 * SZ_64K)
70
71 /* SPI LCDC device structure */
72 struct spi_device *ea3250_spi_lcd_dev = NULL;
73
74 /*
75  * Tick LED
76  */
77 static struct gpio_led phy_leds[] = {
78         {
79                 .name                   = "led0",
80                 .gpio                   = LED_GPIO,
81                 .active_low             = 1,
82                 .default_trigger        = "heartbeat",
83         },
84 };
85
86 static struct gpio_led_platform_data led_data = {
87         .leds = phy_leds,
88         .num_leds = ARRAY_SIZE(phy_leds),
89 };
90
91 static struct platform_device lpc32xx_gpio_led_device = {
92         .name                   = "leds-gpio",
93         .id                     = -1,
94         .dev.platform_data      = &led_data,
95 };
96
97 static struct pca9532_platform_data ea3250_leds = {
98         .leds = {
99         {       .type = PCA9532_TYPE_NONE }, /* Key 1 */
100         {       .type = PCA9532_TYPE_NONE }, /* Key 2 */
101         {       .type = PCA9532_TYPE_NONE }, /* Key 3 */
102         {       .type = PCA9532_TYPE_NONE }, /* Key 4 */
103         {       .type = PCA9532_TYPE_NONE }, /* MMC CD */
104         {       .type = PCA9532_TYPE_NONE }, /* MMC WP */
105         {       .type = PCA9532_TYPE_NONE }, /* not used */
106         {       .type = PCA9532_TYPE_NONE }, /* not used */
107         {       .name = "eabb:red:led1",
108                 .state = PCA9532_OFF,
109                 .type = PCA9532_TYPE_LED,
110         },
111         {       .name = "eabb:red:led2",
112                 .state = PCA9532_OFF,
113                 .type = PCA9532_TYPE_LED,
114         },
115         {       .name = "eabb:red:led3",
116                 .state = PCA9532_OFF,
117                 .type = PCA9532_TYPE_LED,
118         },
119         {       .name = "eabb:red:led4",
120                 .state = PCA9532_OFF,
121                 .type = PCA9532_TYPE_LED,
122         },
123         {       .name = "eabb:red:led5",
124                 .state = PCA9532_OFF,
125                 .type = PCA9532_TYPE_LED,
126         },
127         {       .name = "eabb:red:led6",
128                 .state = PCA9532_OFF,
129                 .type = PCA9532_TYPE_LED,
130         },
131         {       .name = "eabb:red:led7",
132                 .state = PCA9532_OFF,
133                 .type = PCA9532_TYPE_LED,
134         },
135         {       .name = "eabb:red:led8",
136                 .state = PCA9532_OFF,
137                 .type = PCA9532_TYPE_LED,
138         }, },
139         .psc = { 0, 0 },
140         .pwm = { 0, 0 },
141 };
142
143 /*
144  * AMBA SSP (SPI)
145  */
146 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
147         .bus_id                 = 0,
148         .num_chipselect         = 2,
149         .enable_dma             = 0,
150 };
151
152 static struct amba_device lpc32xx_ssp0_device = {
153         .dev    = {
154                 .coherent_dma_mask      = ~0,
155                 .init_name              = "dev:ssp0",
156                 .platform_data          = &lpc32xx_ssp0_data,
157         },
158         .res                            = {
159                 .start                  = LPC32XX_SSP0_BASE,
160                 .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
161                 .flags                  = IORESOURCE_MEM,
162         },
163         .dma_mask                       = ~0,
164         .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
165 };
166
167 /*
168  * Touchscreen device
169  */
170 /* Touch screen chip select function */
171 static void ea3250_spi_cs_set(u32 control)
172 {
173         gpio_set_value(SPI0_CS_GPIO, (int) control);
174 }
175
176 /* Touch screen SPI parameters */
177 static struct pl022_config_chip spi0_chip_info = {
178         .lbm                    = LOOPBACK_DISABLED,
179         .com_mode               = INTERRUPT_TRANSFER,
180         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
181         .hierarchy              = SSP_MASTER,
182         .slave_tx_disable       = 0,
183         .endian_tx              = SSP_TX_LSB,
184         .endian_rx              = SSP_RX_LSB,
185         .data_size              = SSP_DATA_BITS_8,
186         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
187         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
188         .clk_phase              = SSP_CLK_FIRST_EDGE,
189         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
190         .ctrl_len               = SSP_BITS_8,
191         .wait_state             = SSP_MWIRE_WAIT_ZERO,
192         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
193         .cs_control             = ea3250_spi_cs_set,
194 };
195
196 /* Touch screen interrupt status function */
197 static int ea3250_ads7846_pendown_state(void)
198 {
199         u32 tmp = gpio_get_value(ADS_TS_GPIO);
200         return (tmp == 0);
201 }
202
203 /* Touch screen platform data */
204 static struct ads7846_platform_data ea_ads7846_platform_data __initdata = {
205         .debounce_max   = 10,
206         .debounce_tol   = 3,
207         .pressure_max   = 1024,
208         .get_pendown_state = ea3250_ads7846_pendown_state,
209         .wakeup = true,
210 };
211
212 /*
213  * SPI based LCDC data
214  */
215 /* LCDC chip select function */
216 static void ea3250_spi_lcdc_cs_set(u32 control)
217 {
218         gpio_set_value(LCD_CS_GPIO, (int) control);
219 }
220
221 /* LCDC SPI parameters */
222 static struct pl022_config_chip spi0_chip_info1 = {
223         .lbm                    = LOOPBACK_DISABLED,
224         .com_mode               = INTERRUPT_TRANSFER,
225         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
226         .hierarchy              = SSP_MASTER,
227         .slave_tx_disable       = 0,
228         .endian_tx              = SSP_TX_LSB,
229         .endian_rx              = SSP_RX_LSB,
230         .data_size              = SSP_DATA_BITS_8,
231         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
232         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
233         .clk_phase              = SSP_CLK_FIRST_EDGE,
234         .clk_pol                = SSP_CLK_POL_IDLE_LOW,
235         .ctrl_len               = SSP_BITS_8,
236         .wait_state             = SSP_MWIRE_WAIT_ZERO,
237         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
238         .cs_control             = ea3250_spi_lcdc_cs_set,
239 };
240
241 /* SPI devices registration */
242 static int __init ea3250_spi_devices_register(void)
243 {
244 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
245         static struct spi_board_info info[] = {
246                 {
247                         .modalias = "spidev",
248                         .max_speed_hz = 2500000,
249                         .bus_num = 0,
250                         .chip_select = 0,
251                         .controller_data = &spi0_chip_info,
252                 },
253         };
254 #else
255         struct spi_board_info info[] = {
256                 {
257                         .modalias      = "ads7846",
258                         .max_speed_hz  = 2500000,
259                         .chip_select   = 0,
260                         .irq           = IRQ_LPC32XX_GPIO_00,
261                         .platform_data = &ea_ads7846_platform_data,
262                         .controller_data = &spi0_chip_info,
263                 },
264                 {
265                         .modalias      = "ea3250_lcdc",
266                         .max_speed_hz  = 10000000,
267                         .chip_select   = 1,
268                         .controller_data = &spi0_chip_info1,
269                 },
270         };
271 #endif
272
273         /* Configure ADS TS INT GPIO pin as input */
274         if (gpio_request(ADS_TS_GPIO, "ADS7846 TS INT"))
275                 return -EIO;
276         if(gpio_direction_input(ADS_TS_GPIO))
277                 return -EIO;
278
279         /* Configure LCDC CS GPIO pin */
280         if (gpio_request(LCD_CS_GPIO, "LCDC CS"))
281                 return -EIO;
282         if(gpio_direction_output(LCD_CS_GPIO, 1))
283                 return -EIO;
284
285         return spi_register_board_info(info, ARRAY_SIZE(info));
286 }
287 arch_initcall(ea3250_spi_devices_register);
288
289 #if defined (CONFIG_FB_ARMCLCD)
290 /*
291  * LCDC AMBA Driver Board Functions
292  */
293 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
294 /*
295  * Support for Embedded Artists 3.2 inch QVGA LCD panel
296  */
297 static struct clcd_panel conn_lcd_panel = {
298         .mode           = {
299                 .name           = "QVGA portrait",
300                 .refresh        = 60,
301                 .xres           = 240,
302                 .yres           = 320,
303                 .pixclock       = 121654,
304                 .left_margin    = 28,
305                 .right_margin   = 10,
306                 .upper_margin   = 2,
307                 .lower_margin   = 2,
308                 .hsync_len      = 3,
309                 .vsync_len      = 2,
310                 .sync           = 0,
311                 .vmode          = FB_VMODE_NONINTERLACED,
312         },
313         .width          = -1,
314         .height         = -1,
315         .tim2           = (TIM2_IVS | TIM2_IHS),
316         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
317                                 CNTL_LCDBPP16_565),
318         .bpp            = 16,
319 };
320
321 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
322 /*
323  * Support for Embedded Artists 2.8 inch QVGA OLED panel
324 */
325 static struct clcd_panel conn_lcd_panel = {
326         .mode           = {
327                 .name           = "QVGA portrait",
328                 .refresh        = 60,
329                 .xres           = 240,
330                 .yres           = 320,
331                 .pixclock       = 176366,
332                 .left_margin    = 33,
333                 .right_margin   = 26,
334                 .upper_margin   = 3,
335                 .lower_margin   = 8,
336                 .hsync_len      = 32,
337                 .vsync_len      = 4,
338                 .sync           = 0,
339                 .vmode          = FB_VMODE_NONINTERLACED,
340         },
341         .width          = -1,
342         .height         = -1,
343         .tim2           = (TIM2_IVS | TIM2_IHS),
344         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
345                                 CNTL_LCDBPP16_565),
346         .bpp            = 16,
347 };
348 #endif
349
350 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
351 {
352         dma_addr_t dma;
353
354         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
355                         PANEL_SIZE, &dma, GFP_KERNEL);
356         if (!fb->fb.screen_base) {
357                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
358                 return -ENOMEM;
359         }
360
361         fb->fb.fix.smem_start = dma;
362         fb->fb.fix.smem_len = PANEL_SIZE;
363         fb->panel = &conn_lcd_panel;
364
365         if (gpio_request(SSEL0_GPIO5, "Unused GPIO5 input"))
366                 return -EIO;
367         if(gpio_direction_input(SSEL0_GPIO5))
368                 return -EIO;
369
370         /* Configure LCDC RS GPIO pin */
371         if (gpio_request(LCD_RS_GPIO, "LCDC RS"))
372                 return -EIO;
373
374         if(gpio_direction_output(LCD_RS_GPIO, 1))
375                 return -EIO;
376
377         /* Configure LCDC Backlight GPIO pin */
378         if (gpio_request(BKL_POW_GPIO, "LCDC BKL"))
379                 return -EIO;
380
381 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
382         if(gpio_direction_output(BKL_POW_GPIO, 0)) {
383 #else
384         if(gpio_direction_output(BKL_POW_GPIO, 1)) {
385 #endif
386                 return -EIO;
387         }
388
389         return 0;
390 }
391
392 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
393 {
394         return dma_mmap_writecombine(&fb->dev->dev, vma,
395                                      fb->fb.screen_base,
396                                      fb->fb.fix.smem_start,
397                                      fb->fb.fix.smem_len);
398 }
399
400 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
401 {
402         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
403                               fb->fb.screen_base, fb->fb.fix.smem_start);
404 }
405
406 static void spiSend(u8 *buf, size_t len)
407 {
408         BUG_ON(ea3250_spi_lcd_dev == NULL);
409         spi_write(ea3250_spi_lcd_dev, buf, len);
410 }
411
412 #if defined (CONFIG_EA3250_QVGA_2_8_OLED)
413 static void writeToDisp(u16 data)
414 {
415         u8 buf[3];
416
417         /* Initiliase buffer */
418         buf[0] = 0x72;
419         buf[1] = data >> 8;
420         buf[2] = data & 0xff;
421         spiSend(buf, 3);
422 }
423 #endif
424
425 static void writeToReg(u16 addr, u16 data)
426 {
427         u8 buf[3];
428
429 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
430         RESET_RS;
431         buf[0] = 0x00;
432         buf[1] = addr & 0xff;
433         spiSend(buf, 2);
434
435         SET_RS;
436         buf[0] = data >> 8;
437         buf[1] = data & 0xff;
438         spiSend(buf, 2);
439
440         RESET_RS;
441         buf[0] = 0x00;
442         buf[1] = 0x22;
443         spiSend(buf, 2);
444 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
445         buf[0] = 0x70;
446         buf[1] = data >> 8;
447         buf[2] = data & 0xff;
448         spiSend(buf, 3);
449 #endif
450
451 }
452
453 static void clcd_display_init(void)
454 {
455         u32 tmp;
456
457         /* setup MUX register to use SSP0 */
458         __raw_writel(( _BIT(12) | _BIT(10) | _BIT(9) ), LPC32XX_GPIO_P_MUX_SET);
459         tmp = __raw_readl(LPC32XX_GPIO_P_MUX_SET);
460
461 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
462
463         writeToReg (0x00,0x0001);
464         mdelay(20);
465         writeToReg (0x03,0xA2A4);
466         writeToReg (0x0C,0x0004);
467         writeToReg (0x0D,0x0308);
468         writeToReg (0x0E,0x3000);
469         mdelay(50);
470         writeToReg (0x1E,0x00AF);
471         writeToReg (0x01,0x2B3F);
472         writeToReg (0x02,0x0600);
473         writeToReg (0x10,0x0000);
474         writeToReg (0x07,0x0233);
475         writeToReg (0x0B,0x0039);
476         writeToReg (0x0F,0x0000);
477         mdelay(50);
478
479         writeToReg (0x30,0x0707);
480         writeToReg (0x31,0x0204);
481         writeToReg (0x32,0x0204);
482         writeToReg (0x33,0x0502);
483         writeToReg (0x34,0x0507);
484         writeToReg (0x35,0x0204);
485         writeToReg (0x36,0x0204);
486         writeToReg (0x37,0x0502);
487         writeToReg (0x3A,0x0302);
488         writeToReg (0x3B,0x0302);
489
490         writeToReg (0x23,0x0000);
491         writeToReg (0x24,0x0000);
492
493         writeToReg (0x48,0x0000);
494         writeToReg (0x49,0x013F);
495         writeToReg (0x4A,0x0000);
496         writeToReg (0x4B,0x0000);
497
498         writeToReg (0x41,0x0000);
499         writeToReg (0x42,0x0000);
500
501         writeToReg (0x44,0xEF00);
502         writeToReg (0x45,0x0000);
503         writeToReg (0x46,0x013F);
504         mdelay(50);
505
506         writeToReg (0x44,0xEF00);
507         writeToReg (0x45,0x0000);
508         writeToReg (0x4E,0x0000);
509         writeToReg (0x4F,0x0000);
510         writeToReg (0x46,0x013F);
511
512 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
513
514         writeToReg(0,0x02);
515         writeToDisp(0x0192);
516
517         writeToReg(0,0x03);
518         writeToDisp(0x0130);
519
520         /* set standby off */
521         writeToReg(0,0x10);
522         writeToDisp(0x0000);
523
524         mdelay(100);
525
526         /* set display on */
527         writeToReg(0,0x05);
528         writeToDisp(0x0001);
529
530         /* enable image data transfer */
531         writeToReg(0,0x22);
532 #endif
533 }
534
535 void clcd_disable(struct clcd_fb *fb)
536 {
537         /* Disable the backlight */
538 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
539         gpio_set_value(BKL_POW_GPIO, 1);
540 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
541         gpio_set_value(BKL_POW_GPIO, 0);
542 #endif
543 }
544
545 void clcd_enable(struct clcd_fb *fb)
546 {
547         clcd_display_init();
548
549         /* Enable the backlight */
550 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
551         gpio_set_value(BKL_POW_GPIO, 0);
552 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
553         gpio_set_value(BKL_POW_GPIO, 1);
554 #endif
555
556 }
557
558 struct clcd_board lpc32xx_clcd_data = {
559 #if defined (CONFIG_EA3250_QVGA_3_2_LCD)
560         .name           = "Embedded Artists 3.2 inch LCD",
561 #elif defined (CONFIG_EA3250_QVGA_2_8_OLED)
562         .name           = "Embedded Artists 2.8 inch OLED",
563 #else
564         .name           = "Unknown Display",
565 #endif
566         .check          = clcdfb_check,
567         .decode         = clcdfb_decode,
568         .disable        = clcd_disable,
569         .enable         = clcd_enable,
570         .setup          = lpc32xx_clcd_setup,
571         .mmap           = lpc32xx_clcd_mmap,
572         .remove         = lpc32xx_clcd_remove,
573 };
574
575 struct amba_device lpc32xx_clcd_device = {
576         .dev                            = {
577                 .coherent_dma_mask      = ~0,
578                 .init_name              = "dev:clcd",
579                 .platform_data          = &lpc32xx_clcd_data,
580         },
581         .res                            = {
582                 .start                  = LPC32XX_LCD_BASE,
583                 .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
584                 .flags                  = IORESOURCE_MEM,
585         },
586         .dma_mask                       = ~0,
587         .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
588 };
589 #endif
590
591 /*
592  * SPI LCDC Driver Probe function
593  */
594 static int ea3250_spi_lcdc_probe(struct spi_device *spi)
595 {
596         int err;
597
598         spi->mode = SPI_MODE_0;
599         ea3250_spi_lcd_dev = spi;
600
601         /* SPI settings */
602         err = spi_setup(spi);
603         if (err < 0) {
604                 dev_err(&spi->dev, "Err in setting SPI \n");
605                 return err;
606         }
607         return 0;
608 }
609
610 /*
611  *  * SPI LCDC Driver remove function
612  *   * */
613 static int ea3250_spi_lcdc_remove(struct spi_device *spi)
614 {
615         return 0;
616 }
617
618 static struct spi_driver ea3250_spi_lcdc_driver = {
619         .driver = {
620                 .name   = "ea3250_lcdc",
621                 .bus    = &spi_bus_type,
622                 .owner  = THIS_MODULE,
623         },
624         .probe  = ea3250_spi_lcdc_probe,
625         .remove = __devexit_p(ea3250_spi_lcdc_remove),
626 };
627
628 void __init ea3250_spi_lcdc_drv_init(void)
629 {
630         spi_register_driver(&ea3250_spi_lcdc_driver);
631 }
632
633 #if defined (CONFIG_MMC_ARMMMCI)
634
635 /*
636  * Returns !0 when card is removed, 0 when present
637  */
638 unsigned int mmc_card_detect(struct device *dev)
639 {
640         /*
641          * This function may be adapted to retrieve the actual 'card detect'
642          * status over the I2C bus, from PCA9532 pin 8 (LED4). For now, simply
643          * indicate that a card is always present.
644         */
645         return 0;
646 }
647
648 /*
649  * Enable or disable SD slot power
650  */
651 void mmc_power_enable(int enable)
652 {
653         if (enable != 0)
654         {
655                 /* active low */
656                 gpio_set_value(MMC_POWER_GPIO,0);
657         }
658         else
659         {
660                 gpio_set_value(MMC_POWER_GPIO,0);
661         }
662 }
663
664 /*
665  * Board specific MMC driver data
666  */
667 struct mmci_platform_data lpc32xx_plat_data = {
668         .ocr_mask       = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34,
669         .translate_vdd  = NULL,
670         .capabilities   = MMC_CAP_4_BIT_DATA,
671         /*
672          * Indicate no direct GPIO, so MMC driver will assume card is NOT
673          * write-protected
674          */
675         .gpio_wp        = -ENOSYS,
676         /*
677          * Indicate no direct GPIO, so MMC driver will call 'status' callback
678          * function
679          */
680         .gpio_cd        = -ENOSYS,
681         /*
682          * Callback function, used by MMC driver in case 'gpio_cd'
683          * equals -ENOSYS
684          */
685         .status         = mmc_card_detect,
686 };
687
688 /*
689  * SD card controller resources
690  */
691 struct amba_device lpc32xx_mmc_device = {
692         .dev                            = {
693                 .coherent_dma_mask      = ~0,
694                 .init_name              = "dev:mmc0",
695                 .platform_data          = &lpc32xx_plat_data,
696         },
697         .res                            = {
698                 .start                  = LPC32XX_SD_BASE,
699                 .end                    = (LPC32XX_SD_BASE + SZ_4K - 1),
700                 .flags                  = IORESOURCE_MEM,
701         },
702         .dma_mask                       = ~0,
703         .irq                            = {IRQ_LPC32XX_SD0, IRQ_LPC32XX_SD1},
704 };
705 #endif
706
707 /* AMBA based devices list */
708 static struct amba_device *amba_devs[] __initdata = {
709         &lpc32xx_ssp0_device,
710 #if defined (CONFIG_FB_ARMCLCD)
711         &lpc32xx_clcd_device,
712 #endif
713 #if defined (CONFIG_MMC_ARMMMCI)
714         &lpc32xx_mmc_device,
715 #endif
716 };
717
718 /*
719  * Register AMBA BUS Devices.
720  * Call AMBA device restration after SPI driver probe(),
721  * as LCD controller uses SPI driver for initialization
722  */
723 static int __init ea3250_amba_devices_register(void)
724 {
725         u32 i = 0;
726
727         /* Add AMBA devices */
728         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
729                 struct amba_device *d = amba_devs[i];
730                 amba_device_register(d, &iomem_resource);
731         }
732
733         return 0;
734 }
735 device_initcall_sync(ea3250_amba_devices_register);
736
737 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
738 /*
739  *  * Board specific NAND setup data
740  *   */
741 static int nandwp_enable(int enable)
742 {
743         if (enable != 0)
744                 gpio_set_value(NAND_WP_GPIO,0);
745         else
746                 gpio_set_value(NAND_WP_GPIO,1);
747
748         return 1;
749 }
750 #define BLK_SIZE (2048 * 64)
751 static struct mtd_partition ea3250_nand_partition[] = {
752         {
753                 .name   = "ea3250-boot",
754                 .offset = 0,
755                 .size   = (BLK_SIZE * 4),
756                 .mask_flags   = MTD_WRITEABLE,
757         },
758         {
759                 .name   = "ea3250-uboot",
760                 .offset = MTDPART_OFS_APPEND,
761                 .size   = (BLK_SIZE * 6)
762         },
763         {
764                 .name   = "ea3250-kernel",
765                 .offset = MTDPART_OFS_APPEND,
766                 .size   = (BLK_SIZE * 32)
767         },
768         {
769                 .name   = "ea3250-jffs2",
770                 .offset = MTDPART_OFS_APPEND,
771                 .size   = MTDPART_SIZ_FULL
772         },
773 };
774 static struct mtd_partition * ea3250_nand_partitions(int size, int *num_partitions)
775 {
776         *num_partitions = ARRAY_SIZE(ea3250_nand_partition);
777         return ea3250_nand_partition;
778 }
779 struct lpc32XX_nand_cfg lpc32xx_nandcfg =
780 {
781         .wdr_clks               = 14,
782         .wwidth                 = 260000000,
783         .whold                  = 104000000,
784         .wsetup                 = 200000000,
785         .rdr_clks               = 14,
786         .rwidth                 = 34666666,
787         .rhold                  = 104000000,
788         .rsetup                 = 200000000,
789         .use_bbt                = true,
790         .polled_completion      = false,
791         .enable_write_prot      = nandwp_enable,
792         .partition_info         = ea3250_nand_partitions,
793 };
794
795 /*
796  *  * SLC NAND resources
797  *   */
798 static struct resource slc_nand_resources[] = {
799         [0] = {
800                 .start  = LPC32XX_SLC_BASE,
801                 .end    = LPC32XX_SLC_BASE + SZ_4K - 1,
802                 .flags  = IORESOURCE_MEM,
803         },
804
805         [1] = {
806                 .start  = IRQ_LPC32XX_FLASH,
807                 .end    = IRQ_LPC32XX_FLASH,
808                 .flags  = IORESOURCE_IRQ,
809         },
810
811 };
812
813 static u64 lpc32xx_slc_dma_mask = 0xffffffffUL;
814 static struct platform_device lpc32xx_slc_nand_device = {
815         .name           = "lpc32xx-nand",
816         .id             = 0,
817         .dev            = {
818                                 .platform_data  = &lpc32xx_nandcfg,
819                                 .dma_mask    = &lpc32xx_slc_dma_mask,
820                                 .coherent_dma_mask = ~0UL,
821
822         },
823         .num_resources  = ARRAY_SIZE(slc_nand_resources),
824         .resource       = slc_nand_resources,
825 };
826 #endif
827
828 /*
829  * Network Support
830  */
831 static struct lpc_net_cfg lpc32xx_netdata =
832 {
833         .phy_irq        = -1,
834         .phy_mask       = 0xFFFFFFF0,
835 };
836
837 static struct resource net_resources[] = {
838         [0] = {
839                 .start  = LPC32XX_ETHERNET_BASE,
840                 .end    = LPC32XX_ETHERNET_BASE + SZ_4K - 1,
841                 .flags  = IORESOURCE_MEM,
842         },
843
844         [1] = {
845                 .start  = IRQ_LPC32XX_ETHERNET,
846                 .end    = IRQ_LPC32XX_ETHERNET,
847                 .flags  = IORESOURCE_IRQ,
848         },
849
850 };
851
852 static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
853 static struct platform_device lpc32xx_net_device = {
854         .name           = "lpc-net",
855         .id             = 0,
856         .dev            = {
857                 .dma_mask = &lpc32xx_mac_dma_mask,
858                 .coherent_dma_mask = 0xffffffffUL,
859                 .platform_data  = &lpc32xx_netdata,
860         },
861         .num_resources  = ARRAY_SIZE(net_resources),
862         .resource       = net_resources,
863 };
864
865 /*
866  * I2C devices support
867  */
868 #if defined (CONFIG_LEDS_PCA9532) || defined (CONFIG_AT24)
869         static struct i2c_board_info __initdata ea3250_i2c_board_info [] = {
870 #if defined (CONFIG_LEDS_PCA9532)
871                 {
872                         I2C_BOARD_INFO("pca9532", I2C_PCA9532_ADDR),
873                         .platform_data = &ea3250_leds,
874                 },
875 #endif
876 #if defined (CONFIG_AT24)
877                 {
878                         I2C_BOARD_INFO("24c256", I2C_24LC256_ADDR),
879                 },
880 #endif
881         };
882 #endif
883
884 static struct platform_device* ea3250_devs[] __initdata = {
885         &lpc32xx_i2c0_device,
886         &lpc32xx_i2c1_device,
887         &lpc32xx_i2c2_device,
888         &lpc32xx_watchdog_device,
889         &lpc32xx_gpio_led_device,
890         &lpc32xx_rtc_device,
891         &lpc32xx_net_device,
892 #if defined(CONFIG_MTD_NAND_SLC_LPC32XX)
893         &lpc32xx_slc_nand_device,
894 #endif
895 #if defined(CONFIG_USB_OHCI_HCD)
896         &lpc32xx_ohci_device,
897 #endif
898 #if defined(CONFIG_USB_GADGET_LPC32XX)
899         &lpc32xx_usbd_device,
900 #endif
901 };
902
903 extern void __init ea3250_spi_lcdc_drv_init(void);
904
905 /*
906  * Board specific functions
907  */
908 void __init ea3250_board_init(void)
909 {
910         u32 tmp;
911
912         /* Intiliase GPIO */
913         lpc32xx_gpio_init();
914
915 #if defined (CONFIG_MMC_ARMMMCI)
916         /* Enable SD slot power */
917         mmc_power_enable(1);
918 #endif
919
920         /* Set SPI CS GPIO to output */
921         gpio_request(SPI0_CS_GPIO, "spi0 cs");
922         gpio_direction_output(SPI0_CS_GPIO, 1);
923
924         /* Setup network interface for RMII mode */
925         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
926         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
927         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
928         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
929
930         /* Setup SLC NAND controller */
931         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
932                         LPC32XX_CLKPWR_NAND_CLK_CTRL);
933
934         /* Setup LCD muxing to RGB565 */
935         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
936                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
937                                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
938         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
939         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
940
941         /* Set up I2C pull levels */
942         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
943         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
944                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
945         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
946
947         /* Enable DMA for I2S1 channel */
948         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
949         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
950         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
951
952         /* Initalise Serial device */
953         lpc32xx_serial_init();
954
955         /*
956          * AMBA peripheral clocks need to be enabled prior to AMBA device
957          * detection or a data fault will occur, so enable the clocks
958          * here. However, we don't want to enable them if the peripheral
959          * isn't included in the image
960          */
961         /* Initialise SSP clock */
962         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
963         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
964                         LPC32XX_CLKPWR_SSP_CLK_CTRL);
965
966         /* Initialise LCD clock */
967         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
968         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
969                         LPC32XX_CLKPWR_LCDCLK_CTRL);
970
971         /* Enable SD card clock so AMBA driver will work correctly. The
972            AMBA driver needs the clock before the SD card controller
973            driver initializes it. The clock will turn off once the driver
974            has been initialized. */
975         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
976         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
977                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
978         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
979
980         /* Disable UART5->USB transparent mode or USB won't work */
981         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
982         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
983         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
984
985         /* Add platform devcies */
986         platform_add_devices(ea3250_devs, ARRAY_SIZE(ea3250_devs));
987
988         /* Register SPI driver */
989         ea3250_spi_lcdc_drv_init();
990
991         /* Test clock needed for UDA1380 initial init */
992         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
993                         LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
994                         LPC32XX_CLKPWR_TEST_CLK_SEL);
995
996 #if defined (CONFIG_LEDS_PCA9532) || defined (CONFIG_AT24)
997         i2c_register_board_info(0, ea3250_i2c_board_info,
998                         ARRAY_SIZE(ea3250_i2c_board_info));
999 #endif
1000 }
1001
1002 static int __init lpc32xx_display_uid(void)
1003 {
1004         u32 uid[4];
1005
1006         lpc32xx_get_uid(uid);
1007
1008         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
1009                         uid[3], uid[2], uid[1], uid[0]);
1010
1011         return 1;
1012 }
1013 arch_initcall(lpc32xx_display_uid);
1014
1015 MACHINE_START (EA3250, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
1016         /* Maintainer: Embedded Artists */
1017         .phys_io        = LPC32XX_UART5_BASE,
1018         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
1019         .boot_params    = 0x80000100,
1020         .map_io         = lpc32xx_map_io,
1021         .init_irq       = lpc32xx_init_irq,
1022         .timer          = &lpc32xx_timer,
1023         .init_machine   = ea3250_board_init,
1024         MACHINE_END
1025
1026 /* For backwards compatibility with older bootloaders only */
1027 MACHINE_START (LPC3XXX, "Embedded Artists LPC3250 OEM board with the LPC3250 Microcontroller")
1028         /* Maintainer: Embedded Artists */
1029         .phys_io        = LPC32XX_UART5_BASE,
1030         .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
1031         .boot_params    = 0x80000100,
1032         .map_io         = lpc32xx_map_io,
1033         .init_irq       = lpc32xx_init_irq,
1034         .timer          = &lpc32xx_timer,
1035         .init_machine   = ea3250_board_init,
1036         MACHINE_END