arch/arm/mach-lpc32xx/dma.c

   1 /*
   2  *  linux/arch/arm/mach-lpc32xx/ma-lpc32xx.c
   3  *
   4  *  Copyright (C) 2008 NXP Semiconductors
   5  *  (Based on parts of the PNX4008 DMA driver)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/errno.h>
  26 #include <linux/err.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/clk.h>
  29
  30 #include <asm/system.h>
  31 #include <mach/hardware.h>
  32 #include <mach/platform.h>
  33 #include <asm/dma-mapping.h>
  34 #include <asm/io.h>
  35 #include <mach/dma.h>
  36 #include <mach/dmac.h>
  37
  38 #define DMAIOBASE io_p2v(LPC32XX_DMA_BASE)
  39 #define VALID_CHANNEL(c) (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
  40
  41 static DEFINE_SPINLOCK(dma_lock);
  42
  43 struct dma_linked_list {
  44         u32 src;
  45         u32 dest;
  46         u32 next_lli;
  47         u32 ctrl;
  48 };
  49
  50 /* For DMA linked list operation, a linked list of DMA descriptors
  51    is maintained along with some data to manage the list in software. */
  52 struct dma_list_ctrl {
  53         struct dma_linked_list dmall; /* DMA list descriptor */
  54         struct dma_list_ctrl *next_list_addr;   /* Virtual address to next list entry */
  55         struct dma_list_ctrl *prev_list_addr;   /* Virtual address to previous list entry */
  56         u32 next_list_phy;    /* Physical address to next list entry */
  57         u32 prev_list_phy;    /* Physical address to previous list entry */
  58 };
  59
  60 /* Each DMA channel has one of these structures */
  61 struct dma_channel {
  62         char *name;
  63         void (*irq_handler) (int, int, void *);
  64         void *data;
  65         struct dma_config *dmacfg;
  66         u32 control;
  67         u32 config;
  68         u32 config_int_mask;
  69
  70         int list_entries; /* Number of list entries */
  71         u32 list_size; /* Total size of allocated list in bytes */
  72         u32 list_vstart; /* Allocated (virtual) address of list */
  73         u32 list_pstart; /* Allocated (physical) address of list */
  74         int free_entries; /* Number of free descriptors */
  75         struct dma_list_ctrl *list_head, *list_tail;
  76 };
  77
  78 struct dma_control {
  79         struct clk *clk;
  80         int num_clks;
  81         struct dma_channel dma_channels[MAX_DMA_CHANNELS];
  82 };
  83 static struct dma_control dma_ctrl;
  84
  85 static inline void __dma_regs_lock(void)
  86 {
  87         spin_lock_irq(&dma_lock);
  88 }
  89
  90 static inline void __dma_regs_unlock(void)
  91 {
  92         spin_unlock_irq(&dma_lock);
  93 }
  94
  95 static inline void __dma_enable(int ch) {
  96         u32 ch_cfg = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
  97         ch_cfg |= DMAC_CHAN_ENABLE;
  98         __raw_writel(ch_cfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
  99 }
 100
 101 static inline void __dma_disable(int ch) {
 102         u32 ch_cfg = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
 103         ch_cfg &= ~DMAC_CHAN_ENABLE;
 104         __raw_writel(ch_cfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
 105 }
 106
 107 static void dma_clocks_up(void)
 108 {
 109         /* Enable DMA clock if needed */
 110         if (dma_ctrl.num_clks == 0)
 111         {
 112                 clk_enable(dma_ctrl.clk);
 113                 __raw_writel(DMAC_CTRL_ENABLE, DMA_CONFIG(DMAIOBASE));
 114         }
 115
 116         dma_ctrl.num_clks++;
 117 }
 118
 119 static void dma_clocks_down(void)
 120 {
 121         dma_ctrl.num_clks--;
 122
 123         /* Disable DMA clock if needed */
 124         if (dma_ctrl.num_clks == 0)
 125         {
 126                 __raw_writel(0, DMA_CONFIG(DMAIOBASE));
 127                 clk_disable(dma_ctrl.clk);
 128         }
 129 }
 130
 131 static int lpc32xx_ch_setup(struct dma_config *dmachcfg)
 132 {
 133         u32 tmpctrl, tmpcfg, tmp;
 134         int ch = dmachcfg->ch;
 135
 136         /* Channel control setup */
 137         tmpctrl = 0;
 138         switch (dmachcfg->src_size)
 139         {
 140                 case 1:
 141                         tmpctrl |= DMAC_CHAN_SRC_WIDTH_8;
 142                         break;
 143
 144                 case 2:
 145                         tmpctrl |= DMAC_CHAN_SRC_WIDTH_16;
 146                         break;
 147
 148                 case 4:
 149                         tmpctrl |= DMAC_CHAN_SRC_WIDTH_32;
 150                         break;
 151
 152                 default:
 153                         return -EINVAL;
 154         }
 155         switch (dmachcfg->dst_size)
 156         {
 157                 case 1:
 158                         tmpctrl |= DMAC_CHAN_DEST_WIDTH_8;
 159                         break;
 160
 161                 case 2:
 162                         tmpctrl |= DMAC_CHAN_DEST_WIDTH_16;
 163                         break;
 164
 165                 case 4:
 166                         tmpctrl |= DMAC_CHAN_DEST_WIDTH_32;
 167                         break;
 168
 169                 default:
 170                         return -EINVAL;
 171         }
 172         if (dmachcfg->src_inc != 0)
 173         {
 174                 tmpctrl |= DMAC_CHAN_SRC_AUTOINC;
 175         }
 176         if (dmachcfg->dst_inc != 0)
 177         {
 178                 tmpctrl |= DMAC_CHAN_DEST_AUTOINC;
 179         }
 180         if (dmachcfg->src_ahb1 != 0)
 181         {
 182                 tmpctrl |= DMAC_CHAN_SRC_AHB1;
 183         }
 184         if (dmachcfg->dst_ahb1 != 0)
 185         {
 186                 tmpctrl |= DMAC_CHAN_DEST_AHB1;
 187         }
 188         if (dmachcfg->tc_inten != 0)
 189         {
 190                 tmpctrl |= DMAC_CHAN_INT_TC_EN;
 191         }
 192         tmpctrl |= dmachcfg->src_bsize | dmachcfg->dst_bsize;
 193         dma_ctrl.dma_channels[ch].control = tmpctrl;
 194
 195         /* Channel config setup */
 196         tmpcfg = dmachcfg->src_prph | dmachcfg->dst_prph |
 197                 dmachcfg->flowctrl;
 198         dma_ctrl.dma_channels[ch].config = tmpcfg;
 199
 200         dma_ctrl.dma_channels[ch].config_int_mask = 0;
 201         if (dmachcfg->err_inten != 0)
 202         {
 203                 dma_ctrl.dma_channels[ch].config_int_mask |=
 204                         DMAC_CHAN_IE;
 205         }
 206         if (dmachcfg->tc_inten != 0)
 207         {
 208                 dma_ctrl.dma_channels[ch].config_int_mask |=
 209                         DMAC_CHAN_ITC;
 210         }
 211
 212         tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
 213         tmp &= ~DMAC_CHAN_ENABLE;
 214         __raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
 215
 216         /* Clear interrupts for channel */
 217         __raw_writel((1 << ch), DMA_INT_TC_CLEAR(DMAIOBASE));
 218         __raw_writel((1 << ch), DMA_INT_ERR_CLEAR(DMAIOBASE));
 219
 220         /* Write control and config words */
 221         __raw_writel(tmpctrl, DMACH_CONTROL(DMAIOBASE, ch));
 222         __raw_writel(tmpcfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
 223
 224         return 0;
 225 }
 226
 227 int lpc32xx_dma_ch_enable(int ch)
 228 {
 229         if (!VALID_CHANNEL(ch) || !dma_ctrl.dma_channels[ch].name)
 230                 return -EINVAL;
 231
 232         __dma_regs_lock();
 233         __dma_enable(ch);
 234         __dma_regs_unlock();
 235
 236         return 0;
 237 }
 238 EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_enable);
 239
 240 int lpc32xx_dma_ch_disable(int ch)
 241 {
 242         if (!VALID_CHANNEL(ch) || !dma_ctrl.dma_channels[ch].name)
 243                 return -EINVAL;
 244
 245         __dma_regs_lock();
 246         __dma_disable(ch);
 247         __dma_regs_unlock();
 248
 249         return 0;
 250 }
 251 EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_disable);
 252
 253 int lpc32xx_dma_ch_get(struct dma_config *dmachcfg, char *name,
 254                 void *irq_handler, void *data) {
 255         int ret;
 256
 257         if (!VALID_CHANNEL(dmachcfg->ch))
 258                 return -EINVAL;
 259
 260         /* If the channel is already enabled, return */
 261         if (dma_ctrl.dma_channels[dmachcfg->ch].name != NULL)
 262                 return -ENODEV;
 263
 264         /* Save channel data */
 265         dma_ctrl.dma_channels[dmachcfg->ch].dmacfg = dmachcfg;
 266         dma_ctrl.dma_channels[dmachcfg->ch].name = name;
 267         dma_ctrl.dma_channels[dmachcfg->ch].irq_handler = irq_handler;
 268         dma_ctrl.dma_channels[dmachcfg->ch].data = data;
 269
 270         /* Setup channel */
 271         __dma_regs_lock();
 272         dma_clocks_up();
 273         ret = lpc32xx_ch_setup(dmachcfg);
 274         __dma_regs_unlock();
 275
 276         return ret;
 277 }
 278 EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_get);
 279
 280 int lpc32xx_dma_ch_put(int ch)
 281 {
 282         u32 tmp;
 283
 284         if (!VALID_CHANNEL(ch))
 285                 return -EINVAL;
 286
 287         /* If the channel is already disabled, return */
 288         if (dma_ctrl.dma_channels[ch].name == NULL)
 289                 return -EINVAL;
 290
 291         tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
 292         tmp &= ~DMAC_CHAN_ENABLE;
 293         __raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
 294
 295         __dma_regs_lock();
 296         lpc32xx_dma_ch_disable(ch);
 297         dma_clocks_down();
 298         __dma_regs_unlock();
 299
 300         dma_ctrl.dma_channels[ch].name = NULL;
 301
 302         return 0;
 303 }
 304 EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_put);
 305
 306 int lpc32xx_dma_ch_pause_unpause(int ch, int pause) {
 307         u32 tmp;
 308
 309         if (!VALID_CHANNEL(ch))
 310                 return -EINVAL;
 311
 312         /* If the channel is already disabled, return */
 313         if (dma_ctrl.dma_channels[ch].name == NULL)
 314                 return -EINVAL;
 315
 316         tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
 317         if (pause) {
 318                 tmp |= DMAC_CHAN_HALT;
 319         }
 320         else {
 321                 tmp &= ~DMAC_CHAN_HALT;
 322         }
 323         __raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
 324
 325         return 0;
 326 }
 327 EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_pause_unpause);
 328
 329 int lpc32xx_dma_start_pflow_xfer(int ch,
 330                                 void *src,
 331                                 void *dst,
 332                                 int enable)
 333 {
 334         u32 tmp;
 335
 336         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL))
 337                 return -EINVAL;
 338
 339         /* When starting a DMA transfer where the peripheral is the flow
 340            controller, DMA must be previously disabled */
 341         tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
 342         if (tmp & DMAC_CHAN_ENABLE)
 343                 return -EBUSY;
 344
 345         __dma_regs_lock();
 346         __raw_writel((u32) src, DMACH_SRC_ADDR(DMAIOBASE, ch));
 347         __raw_writel((u32) dst, DMACH_DEST_ADDR(DMAIOBASE, ch));
 348         __raw_writel(0, DMACH_LLI(DMAIOBASE, ch));
 349         __raw_writel(dma_ctrl.dma_channels[ch].control, DMACH_CONTROL(DMAIOBASE, ch));
 350
 351         tmp = dma_ctrl.dma_channels[ch].config |
 352                 dma_ctrl.dma_channels[ch].config_int_mask;
 353         if (enable != 0)
 354                 tmp |= DMAC_CHAN_ENABLE;
 355         __raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
 356
 357         __dma_regs_unlock();
 358
 359         return 0;
 360 }
 361 EXPORT_SYMBOL_GPL(lpc32xx_dma_start_pflow_xfer);
 362
 363 extern u32 lpc32xx_dma_llist_v_to_p(int ch,
 364                                     u32 vlist) {
 365         u32 pptr;
 366
 367         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
 368                 (dma_ctrl.dma_channels[ch].list_vstart == 0))
 369                 return 0;
 370
 371         pptr = vlist - dma_ctrl.dma_channels[ch].list_vstart;
 372         pptr += dma_ctrl.dma_channels[ch].list_pstart;
 373
 374         return pptr;
 375 }
 376 EXPORT_SYMBOL_GPL(lpc32xx_dma_llist_v_to_p);
 377
 378 u32 lpc32xx_dma_llist_p_to_v(int ch,
 379                              u32 plist) {
 380         u32 vptr;
 381
 382         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
 383                 (dma_ctrl.dma_channels[ch].list_vstart == 0))
 384                 return 0;
 385
 386         vptr = plist - dma_ctrl.dma_channels[ch].list_pstart;
 387         vptr += dma_ctrl.dma_channels[ch].list_vstart;
 388
 389         return vptr;
 390 }
 391 EXPORT_SYMBOL_GPL(lpc32xx_dma_llist_p_to_v);
 392
 393 u32 lpc32xx_dma_alloc_llist(int ch,
 394                              int entries) {
 395         int i;
 396         dma_addr_t dma_handle;
 397         struct dma_list_ctrl *pdmalist, *pdmalistst;
 398
 399         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL))
 400                 return 0;
 401
 402         /* Limit number of list entries */
 403         if (entries < 2) {
 404                 entries = 2;
 405         }
 406         if (entries > 64) {
 407                 entries = 64;
 408         }
 409
 410         /* Save list information */
 411         dma_ctrl.dma_channels[ch].list_entries = entries;
 412         dma_ctrl.dma_channels[ch].list_size = (entries * sizeof(struct dma_list_ctrl));
 413         dma_ctrl.dma_channels[ch].list_vstart = (u32) dma_alloc_coherent(NULL,
 414                 dma_ctrl.dma_channels[ch].list_size, &dma_handle, GFP_KERNEL);
 415         if (dma_ctrl.dma_channels[ch].list_vstart == 0) {
 416                 /* No allocated DMA space */
 417                 return 0;
 418         }
 419         dma_ctrl.dma_channels[ch].list_pstart = (u32) dma_handle;
 420
 421         /* Setup list tail and head pointers */
 422         pdmalist = pdmalistst = (struct dma_list_ctrl *) dma_ctrl.dma_channels[ch].list_vstart;
 423         for (i = 0; i < entries; i++) {
 424                 pdmalistst->next_list_addr = pdmalistst + 1;
 425                 pdmalistst->prev_list_addr = pdmalistst - 1;
 426                 pdmalistst->next_list_phy = lpc32xx_dma_llist_v_to_p(ch, (u32) pdmalistst->next_list_addr);
 427                 pdmalistst->prev_list_phy = lpc32xx_dma_llist_v_to_p(ch, (u32) pdmalistst->prev_list_addr);
 428                 pdmalistst++;
 429         }
 430         pdmalist[entries - 1].next_list_addr = pdmalist;
 431         pdmalist[entries - 1].next_list_phy = lpc32xx_dma_llist_v_to_p(ch,
 432                 (u32) pdmalist[entries - 1].next_list_addr);
 433         pdmalist->prev_list_addr = &pdmalist[entries - 1];
 434         pdmalist->prev_list_phy = lpc32xx_dma_llist_v_to_p(ch, (u32) pdmalist->prev_list_addr);
 435
 436         /* Save current free descriptors and current head/tail */
 437         dma_ctrl.dma_channels[ch].free_entries = entries;
 438         dma_ctrl.dma_channels[ch].list_head = pdmalist;
 439         dma_ctrl.dma_channels[ch].list_tail = pdmalist;
 440
 441         return dma_ctrl.dma_channels[ch].list_vstart;
 442 }
 443 EXPORT_SYMBOL_GPL(lpc32xx_dma_alloc_llist);
 444
 445 void lpc32xx_dma_dealloc_llist(int ch) {
 446
 447         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
 448                 (dma_ctrl.dma_channels[ch].list_vstart == 0))
 449                 return;
 450
 451         dma_free_coherent(NULL, dma_ctrl.dma_channels[ch].list_size,
 452                 (void *) dma_ctrl.dma_channels[ch].list_vstart,
 453                 (dma_addr_t) dma_ctrl.dma_channels[ch].list_pstart);
 454         dma_ctrl.dma_channels[ch].list_head = 0;
 455         dma_ctrl.dma_channels[ch].list_tail = 0;
 456         dma_ctrl.dma_channels[ch].list_entries = 0;
 457         dma_ctrl.dma_channels[ch].free_entries = 0;
 458         dma_ctrl.dma_channels[ch].list_vstart = 0;
 459 }
 460 EXPORT_SYMBOL_GPL(lpc32xx_dma_dealloc_llist);
 461
 462 extern u32 lpc32xx_dma_get_llist_head(int ch) {
 463         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
 464                 (dma_ctrl.dma_channels[ch].list_vstart == 0))
 465                 return 0;
 466
 467         /* Return the current list pointer (virtual) for the
 468            DMA channel */
 469         return lpc32xx_dma_llist_p_to_v(ch,
 470                 __raw_readl(DMACH_LLI(DMAIOBASE, ch)));
 471 }
 472 EXPORT_SYMBOL_GPL(lpc32xx_dma_get_llist_head);
 473
 474 extern void lpc32xx_dma_flush_llist(int ch) {
 475         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
 476                 (dma_ctrl.dma_channels[ch].list_vstart == 0))
 477                 return;
 478
 479         /* Disable channel and clear LLI */
 480         __dma_regs_lock();
 481         __dma_disable(ch);
 482         __raw_writel(0, DMACH_LLI(DMAIOBASE, ch));
 483         __dma_regs_unlock();
 484
 485         dma_ctrl.dma_channels[ch].list_head = (struct dma_list_ctrl *)
 486                 dma_ctrl.dma_channels[ch].list_vstart;
 487         dma_ctrl.dma_channels[ch].list_tail = (struct dma_list_ctrl *)
 488                 dma_ctrl.dma_channels[ch].list_vstart;
 489         dma_ctrl.dma_channels[ch].free_entries =
 490                 dma_ctrl.dma_channels[ch].list_entries;
 491 }
 492 EXPORT_SYMBOL_GPL(lpc32xx_dma_flush_llist);
 493
 494 u32 lpc32xx_dma_queue_llist_entry(int ch,
 495                                   void *src,
 496                                   void *dst,
 497                                   int size) {
 498         struct dma_list_ctrl *plhead;
 499         u32 ctrl, cfg;
 500
 501         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
 502                 (dma_ctrl.dma_channels[ch].list_vstart == 0))
 503                 return 0;
 504
 505         /* Exit if all the buffers are used */
 506         if (dma_ctrl.dma_channels[ch].free_entries == 0) {
 507                 return 0;
 508         }
 509
 510         /* Next available DMA link descriptor */
 511         plhead = dma_ctrl.dma_channels[ch].list_head;
 512
 513         /* Adjust size to number of transfers (vs bytes) */
 514         size = size / dma_ctrl.dma_channels[ch].dmacfg->dst_size;
 515
 516         /* Setup control and config words */
 517         ctrl = dma_ctrl.dma_channels[ch].control | size;
 518         cfg = dma_ctrl.dma_channels[ch].config | DMAC_CHAN_ENABLE |
 519                 dma_ctrl.dma_channels[ch].config_int_mask;
 520
 521         /* Populate DMA linked data structure */
 522         plhead->dmall.src = (u32) src;
 523         plhead->dmall.dest = (u32) dst;
 524         plhead->dmall.next_lli = 0;
 525         plhead->dmall.ctrl = ctrl;
 526
 527         __dma_regs_lock();
 528
 529         /* Append this link to the end of the previous link */
 530         plhead->prev_list_addr->dmall.next_lli = lpc32xx_dma_llist_v_to_p(ch, (u32) plhead);
 531
 532         /* Decrement available buffers */
 533         dma_ctrl.dma_channels[ch].free_entries--;
 534
 535         /* If the DMA channel is idle, then the buffer needs to be placed directly into
 536            the DMA registers */
 537         if ((__raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch)) & DMAC_CHAN_ENABLE) == 0) {
 538                 /* DMA is disabled, so move the current buffer into the
 539                    channel registers and start transfer */
 540                 __raw_writel((u32) src, DMACH_SRC_ADDR(DMAIOBASE, ch));
 541                 __raw_writel((u32) dst, DMACH_DEST_ADDR(DMAIOBASE, ch));
 542                 __raw_writel(0, DMACH_LLI(DMAIOBASE, ch));
 543                 __raw_writel(ctrl, DMACH_CONTROL(DMAIOBASE, ch));
 544                 __raw_writel(cfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
 545         }
 546
 547         /* Process next link on next call */
 548         dma_ctrl.dma_channels[ch].list_head = plhead->next_list_addr;
 549
 550         __dma_regs_unlock();
 551
 552         return (u32) plhead;
 553 }
 554 EXPORT_SYMBOL_GPL(lpc32xx_dma_queue_llist_entry);
 555
 556 extern u32 lpc32xx_get_free_llist_entry(int ch) {
 557         struct dma_list_ctrl *pltail;
 558
 559         if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
 560                 (dma_ctrl.dma_channels[ch].list_vstart == 0))
 561                 return 0;
 562
 563         /* Exit if no entries to free */
 564         if (dma_ctrl.dma_channels[ch].free_entries ==
 565                 dma_ctrl.dma_channels[ch].list_entries) {
 566                 return 0;
 567         }
 568
 569         /* Get tail pointer */
 570         pltail = dma_ctrl.dma_channels[ch].list_tail;
 571
 572         /* Next tail */
 573         dma_ctrl.dma_channels[ch].list_tail = pltail->next_list_addr;
 574
 575         /* Increment available buffers */
 576         dma_ctrl.dma_channels[ch].free_entries++;
 577
 578         return (u32) pltail;
 579 }
 580 EXPORT_SYMBOL_GPL(lpc32xx_get_free_llist_entry);
 581
 582 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 583 {
 584         int i;
 585         unsigned long dint = __raw_readl(DMA_INT_STAT(DMAIOBASE));
 586         unsigned long tcint = __raw_readl(DMA_INT_TC_STAT(DMAIOBASE));
 587         unsigned long eint = __raw_readl(DMA_INT_ERR_STAT(DMAIOBASE));
 588         unsigned long i_bit;
 589
 590         for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
 591                 i_bit = 1 << i;
 592                 if (dint & i_bit) {
 593                         struct dma_channel *channel = &dma_ctrl.dma_channels[i];
 594
 595                         if (channel->name && channel->irq_handler) {
 596                                 int cause = 0;
 597
 598                                 if (eint & i_bit) {
 599                                         __raw_writel(i_bit, DMA_INT_ERR_CLEAR(DMAIOBASE));
 600                                         cause |= DMA_ERR_INT;
 601                                 }
 602                                 if (tcint & i_bit) {
 603                                         __raw_writel(i_bit, DMA_INT_TC_CLEAR(DMAIOBASE));
 604                                         cause |= DMA_TC_INT;
 605                                 }
 606
 607                                 channel->irq_handler(i, cause, channel->data);
 608                         } else {
 609                                 /*
 610                                  * IRQ for an unregistered DMA channel
 611                                  */
 612                                 __raw_writel(i_bit, DMA_INT_ERR_CLEAR(DMAIOBASE));
 613                                 __raw_writel(i_bit, DMA_INT_TC_CLEAR(DMAIOBASE));
 614                                 printk(KERN_WARNING
 615                                        "spurious IRQ for DMA channel %d\n", i);
 616                         }
 617                 }
 618         }
 619
 620         return IRQ_HANDLED;
 621 }
 622
 623 static int __init lpc32xx_dma_init(void)
 624 {
 625         int ret;
 626
 627         printk(KERN_INFO "LPC32XX DMA driver\n");
 628
 629         ret = request_irq(IRQ_LPC32XX_DMA, dma_irq_handler, 0, "DMA", NULL);
 630         if (ret) {
 631                 printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
 632                 goto out;
 633         }
 634
 635         /* Get DMA clock */
 636         dma_ctrl.clk = clk_get(NULL, "clk_dmac");
 637         if (IS_ERR(dma_ctrl.clk)) {
 638                 ret = -ENODEV;
 639                 goto errout;
 640         }
 641         clk_enable(dma_ctrl.clk);
 642
 643         /* Clear DMA controller */
 644         __raw_writel(1, DMA_CONFIG(DMAIOBASE));
 645         __raw_writel(0xFF, DMA_INT_TC_CLEAR(DMAIOBASE));
 646         __raw_writel(0xFF, DMA_INT_ERR_CLEAR(DMAIOBASE));
 647
 648         /* Clock is only enabled when needed to save power */
 649         clk_disable(dma_ctrl.clk);
 650
 651         return 0;
 652
 653 errout:
 654         free_irq(IRQ_LPC32XX_DMA, NULL);
 655
 656 out:
 657         return ret;
 658 }
 659 arch_initcall(lpc32xx_dma_init);
 660
 661