arch/arm/mach-lpc32xx/clock.c

   1 /*
   2  * arch/arm/mach-lpc32xx/clock.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 /*
  20  * LPC32xx clock management driver overview
  21  *
  22  * The LPC32XX contains a number of high level system clocks that can be
  23  * generated from different sources. These system clocks are used to
  24  * generate the CPU and bus rates and the individual peripheral clocks in
  25  * the system. When Linux is started by the boot loader, the system
  26  * clocks are already running. Stopping a system clock during normal
  27  * Linux operation should never be attempted, as peripherals that require
  28  * those clocks will quit working (ie, DRAM).
  29  *
  30  * The LPC32xx high level clock tree looks as follows. Clocks marked with
  31  * an asterisk are always on and cannot be disabled. Clocks marked with
  32  * an ampersand can only be disabled in CPU suspend mode. Clocks marked
  33  * with a caret are always on if it is the selected clock for the SYSCLK
  34  * source. The clock that isn't used for SYSCLK can be enabled and
  35  * disabled normally.
  36  *                               32KHz oscillator*
  37  *                               /      |      \
  38  *                             RTC*   PLL397^ TOUCH
  39  *                                     /
  40  *               Main oscillator^     /
  41  *                   |        \      /
  42  *                   |         SYSCLK&
  43  *                   |            \
  44  *                   |             \
  45  *                USB_PLL       HCLK_PLL&
  46  *                   |           |    |
  47  *            USB host/device  PCLK&  |
  48  *                               |    |
  49  *                             Peripherals
  50  *
  51  * The CPU and chip bus rates are derived from the HCLK PLL, which can
  52  * generate various clock rates up to 266MHz and beyond. The internal bus
  53  * rates (PCLK and HCLK) are generated from dividers based on the HCLK
  54  * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
  55  * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
  56  * level clocks are based on either HCLK or PCLK, but have their own
  57  * dividers as part of the IP itself. Because of this, the system clock
  58  * rates should not be changed.
  59  *
  60  * The HCLK PLL is clocked from SYSCLK, which can be derived from the
  61  * main oscillator or PLL397. PLL397 generates a rate that is 397 times
  62  * the 32KHz oscillator rate. The main oscillator runs at the selected
  63  * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
  64  * is normally 13MHz, but depends on the selection of external crystals
  65  * or oscillators. If USB operation is required, the main oscillator must
  66  * be used in the system.
  67  *
  68  * Switching SYSCLK between sources during normal Linux operation is not
  69  * supported. SYSCLK is preset in the bootloader. Because of the
  70  * complexities of clock management during clock frequency changes,
  71  * there are some limitations to the clock driver explained below:
  72  * - The PLL397 and main oscillator can be enabled and disabled by the
  73  *   clk_enable() and clk_disable() functions unless SYSCLK is based
  74  *   on that clock. This allows the other oscillator that isn't driving
  75  *   the HCLK PLL to be used as another system clock that can be routed
  76  *   to an external pin.
  77  * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
  78  *   this driver.
  79  * - HCLK and PCLK rates cannot be changed as part of this driver.
  80  * - Most peripherals have their own dividers are part of the peripheral
  81  *   block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
  82  *   will also impact the individual peripheral rates.
  83  */
  84
  85 #include <linux/kernel.h>
  86 #include <linux/list.h>
  87 #include <linux/errno.h>
  88 #include <linux/device.h>
  89 #include <linux/delay.h>
  90 #include <linux/err.h>
  91 #include <linux/clk.h>
  92 #include <linux/amba/bus.h>
  93 #include <linux/amba/clcd.h>
  94
  95 #include <mach/hardware.h>
  96 #include <asm/clkdev.h>
  97 #include <mach/clkdev.h>
  98 #include <mach/platform.h>
  99 #include "clock.h"
 100 #include "common.h"
 101
 102 static int usb_pll_enable, usb_pll_valid;
 103
 104 static struct clk clk_armpll;
 105 static struct clk clk_usbpll;
 106 static DEFINE_MUTEX(clkm_lock);
 107
 108 /*
 109  * Post divider values for PLLs based on selected register value
 110  */
 111 static const u32 pll_postdivs[4] = {1, 2, 4, 8};
 112
 113 static unsigned long local_return_parent_rate(struct clk *clk)
 114 {
 115         /*
 116          * If a clock has a rate of 0, then it inherits it's parent
 117          * clock rate
 118          */
 119         while (clk->rate == 0)
 120                 clk = clk->parent;
 121
 122         return clk->rate;
 123 }
 124
 125 /* 32KHz clock has a fixed rate and is not stoppable */
 126 static struct clk osc_32KHz = {
 127         .rate           = LPC32XX_CLOCK_OSC_FREQ,
 128         .get_rate       = local_return_parent_rate,
 129 };
 130
 131 static int local_pll397_enable(struct clk *clk, int enable)
 132 {
 133         u32 reg;
 134         unsigned long timeout = jiffies + msecs_to_jiffies(10);
 135
 136         reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
 137
 138         if (enable == 0) {
 139                 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
 140                 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
 141         } else {
 142                 /* Enable PLL397 */
 143                 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
 144                 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
 145
 146                 /* Wait for PLL397 lock */
 147                 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
 148                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
 149                         (timeout > jiffies))
 150                         cpu_relax();
 151
 152                 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
 153                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
 154                         return -ENODEV;
 155         }
 156
 157         return 0;
 158 }
 159
 160 static int local_oscmain_enable(struct clk *clk, int enable)
 161 {
 162         u32 reg;
 163         unsigned long timeout = jiffies + msecs_to_jiffies(10);
 164
 165         reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 166
 167         if (enable == 0) {
 168                 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
 169                 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 170         } else {
 171                 /* Enable main oscillator */
 172                 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
 173                 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 174
 175                 /* Wait for main oscillator to start */
 176                 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
 177                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
 178                         (timeout > jiffies))
 179                         cpu_relax();
 180
 181                 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
 182                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
 183                         return -ENODEV;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static struct clk osc_pll397 = {
 190         .parent         = &osc_32KHz,
 191         .enable         = local_pll397_enable,
 192         .rate           = LPC32XX_CLOCK_OSC_FREQ * 397,
 193         .get_rate       = local_return_parent_rate,
 194 };
 195
 196 static struct clk osc_main = {
 197         .enable         = local_oscmain_enable,
 198         .rate           = LPC32XX_MAIN_OSC_FREQ,
 199         .get_rate       = local_return_parent_rate,
 200 };
 201
 202 static struct clk clk_sys;
 203
 204 /*
 205  * Convert a PLL register value to a PLL output frequency
 206  */
 207 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
 208 {
 209         struct clk_pll_setup pllcfg;
 210
 211         pllcfg.cco_bypass_b15 = 0;
 212         pllcfg.direct_output_b14 = 0;
 213         pllcfg.fdbk_div_ctrl_b13 = 0;
 214         if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
 215                 pllcfg.cco_bypass_b15 = 1;
 216         if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
 217                 pllcfg.direct_output_b14 = 1;
 218         if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
 219                 pllcfg.fdbk_div_ctrl_b13 = 1;
 220         pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
 221         pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
 222         pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
 223
 224         return clk_check_pll_setup(inputclk, &pllcfg);
 225 }
 226
 227 /*
 228  * Setup the HCLK PLL with a PLL structure
 229  */
 230 static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
 231 {
 232         u32 tv, tmp = 0;
 233
 234         if (PllSetup->analog_on != 0)
 235                 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
 236         if (PllSetup->cco_bypass_b15 != 0)
 237                 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
 238         if (PllSetup->direct_output_b14 != 0)
 239                 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
 240         if (PllSetup->fdbk_div_ctrl_b13 != 0)
 241                 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
 242
 243         tv = ffs(PllSetup->pll_p) - 1;
 244         if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
 245                 return 0;
 246
 247         tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
 248         tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
 249         tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
 250
 251         return tmp;
 252 }
 253
 254 /*
 255  * Update the ARM core PLL frequency rate variable from the actual PLL setting
 256  */
 257 static void local_update_armpll_rate(void)
 258 {
 259         u32 clkin, pllreg;
 260
 261         clkin = clk_armpll.parent->rate;
 262         pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
 263
 264         clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
 265 }
 266
 267 /*
 268  * Find a PLL configuration for the selected input frequency
 269  */
 270 static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
 271         struct clk_pll_setup *pllsetup)
 272 {
 273         u32 ifreq, freqtol, m, n, p, fclkout;
 274
 275         /* Determine frequency tolerance limits */
 276         freqtol = target_freq / 250;
 277         ifreq = pllin_freq;
 278
 279         /* Is direct bypass mode possible? */
 280         if (abs(pllin_freq - target_freq) <= freqtol) {
 281                 pllsetup->analog_on = 0;
 282                 pllsetup->cco_bypass_b15 = 1;
 283                 pllsetup->direct_output_b14 = 1;
 284                 pllsetup->fdbk_div_ctrl_b13 = 1;
 285                 pllsetup->pll_p = pll_postdivs[0];
 286                 pllsetup->pll_n = 1;
 287                 pllsetup->pll_m = 1;
 288                 return clk_check_pll_setup(ifreq, pllsetup);
 289         } else if (target_freq <= ifreq) {
 290                 pllsetup->analog_on = 0;
 291                 pllsetup->cco_bypass_b15 = 1;
 292                 pllsetup->direct_output_b14 = 0;
 293                 pllsetup->fdbk_div_ctrl_b13 = 1;
 294                 pllsetup->pll_n = 1;
 295                 pllsetup->pll_m = 1;
 296                 for (p = 0; p <= 3; p++) {
 297                         pllsetup->pll_p = pll_postdivs[p];
 298                         fclkout = clk_check_pll_setup(ifreq, pllsetup);
 299                         if (abs(target_freq - fclkout) <= freqtol)
 300                                 return fclkout;
 301                 }
 302         }
 303
 304         /* Is direct mode possible? */
 305         pllsetup->analog_on = 1;
 306         pllsetup->cco_bypass_b15 = 0;
 307         pllsetup->direct_output_b14 = 1;
 308         pllsetup->fdbk_div_ctrl_b13 = 0;
 309         pllsetup->pll_p = pll_postdivs[0];
 310         for (m = 1; m <= 256; m++) {
 311                 for (n = 1; n <= 4; n++) {
 312                         /* Compute output frequency for this value */
 313                         pllsetup->pll_n = n;
 314                         pllsetup->pll_m = m;
 315                         fclkout = clk_check_pll_setup(ifreq,
 316                                 pllsetup);
 317                         if (abs(target_freq - fclkout) <=
 318                                 freqtol)
 319                                 return fclkout;
 320                 }
 321         }
 322
 323         /* Is integer mode possible? */
 324         pllsetup->analog_on = 1;
 325         pllsetup->cco_bypass_b15 = 0;
 326         pllsetup->direct_output_b14 = 0;
 327         pllsetup->fdbk_div_ctrl_b13 = 1;
 328         for (m = 1; m <= 256; m++) {
 329                 for (n = 1; n <= 4; n++) {
 330                         for (p = 0; p < 4; p++) {
 331                                 /* Compute output frequency */
 332                                 pllsetup->pll_p = pll_postdivs[p];
 333                                 pllsetup->pll_n = n;
 334                                 pllsetup->pll_m = m;
 335                                 fclkout = clk_check_pll_setup(
 336                                         ifreq, pllsetup);
 337                                 if (abs(target_freq - fclkout) <= freqtol)
 338                                         return fclkout;
 339                         }
 340                 }
 341         }
 342
 343         /* Try non-integer mode */
 344         pllsetup->analog_on = 1;
 345         pllsetup->cco_bypass_b15 = 0;
 346         pllsetup->direct_output_b14 = 0;
 347         pllsetup->fdbk_div_ctrl_b13 = 0;
 348         for (m = 1; m <= 256; m++) {
 349                 for (n = 1; n <= 4; n++) {
 350                         for (p = 0; p < 4; p++) {
 351                                 /* Compute output frequency */
 352                                 pllsetup->pll_p = pll_postdivs[p];
 353                                 pllsetup->pll_n = n;
 354                                 pllsetup->pll_m = m;
 355                                 fclkout = clk_check_pll_setup(
 356                                         ifreq, pllsetup);
 357                                 if (abs(target_freq - fclkout) <= freqtol)
 358                                         return fclkout;
 359                         }
 360                 }
 361         }
 362
 363         return 0;
 364 }
 365
 366 static struct clk clk_armpll = {
 367         .parent         = &clk_sys,
 368         .get_rate       = local_return_parent_rate,
 369 };
 370
 371 /*
 372  * Setup the USB PLL with a PLL structure
 373  */
 374 static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
 375 {
 376         u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
 377
 378         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
 379         reg |= tmp;
 380         __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 381
 382         return clk_check_pll_setup(clk_usbpll.parent->rate,
 383                 pHCLKPllSetup);
 384 }
 385
 386 static int local_usbpll_enable(struct clk *clk, int enable)
 387 {
 388         u32 reg;
 389         int ret = 0;
 390         unsigned long timeout = jiffies + msecs_to_jiffies(20);
 391
 392         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 393
 394         __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
 395                 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
 396                 LPC32XX_CLKPWR_USB_CTRL);
 397         __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
 398                 LPC32XX_CLKPWR_USB_CTRL);
 399
 400         if (enable && usb_pll_valid && usb_pll_enable) {
 401                 ret = -ENODEV;
 402                 /*
 403                  * If the PLL rate has been previously set, then the rate
 404                  * in the PLL register is valid and can be enabled here.
 405                  * Otherwise, it needs to be enabled as part of setrate.
 406                  */
 407
 408                 /*
 409                  * Gate clock into PLL
 410                  */
 411                 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
 412                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 413
 414                 /*
 415                  * Enable PLL
 416                  */
 417                 reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
 418                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 419
 420                 /*
 421                  * Wait for PLL to lock
 422                  */
 423                 while ((timeout > jiffies) && (ret == -ENODEV)) {
 424                         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 425                         if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
 426                                 ret = 0;
 427                         else
 428                                 udelay(10);
 429                 }
 430
 431                 /*
 432                  * Gate clock from PLL if PLL is locked
 433                  */
 434                 if (ret == 0) {
 435                         __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
 436                                 LPC32XX_CLKPWR_USB_CTRL);
 437                 }
 438                 else {
 439                         __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
 440                                 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
 441                                 LPC32XX_CLKPWR_USB_CTRL);
 442                 }
 443         } else if ((enable == 0) && usb_pll_valid  && usb_pll_enable) {
 444                 usb_pll_valid = 0;
 445                 usb_pll_enable = 0;
 446         }
 447
 448         return ret;
 449 }
 450
 451 static unsigned long local_usbpll_round_rate(struct clk *clk,
 452         unsigned long rate)
 453 {
 454         u32 clkin, usbdiv;
 455         struct clk_pll_setup pllsetup;
 456
 457         /*
 458          * Unlike other clocks, this clock has a KHz input rate, so bump
 459          * it up to work with the PLL function
 460          */
 461         rate = rate * 1000;
 462
 463         clkin = clk->get_rate(clk);
 464         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 465                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 466         clkin = clkin / usbdiv;
 467
 468         /* Try to find a good rate setup */
 469         if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 470                 return 0;
 471
 472         return clk_check_pll_setup(clkin, &pllsetup);
 473 }
 474
 475 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
 476 {
 477         int ret = -ENODEV;
 478         u32 clkin, usbdiv;
 479         struct clk_pll_setup pllsetup;
 480
 481         /*
 482          * Unlike other clocks, this clock has a KHz input rate, so bump
 483          * it up to work with the PLL function
 484          */
 485         rate = rate * 1000;
 486
 487         clkin = clk->get_rate(clk->parent);
 488         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 489                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 490         clkin = clkin / usbdiv;
 491
 492         /* Try to find a good rate setup */
 493         if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 494                 return -EINVAL;
 495
 496         /*
 497          * Disable PLL clocks during PLL change
 498          */
 499         local_usbpll_enable(clk, 0);
 500         pllsetup.analog_on = 0;
 501         local_clk_usbpll_setup(&pllsetup);
 502
 503         /*
 504          * Start USB PLL and check PLL status
 505          */
 506
 507         usb_pll_valid = 1;
 508         usb_pll_enable = 1;
 509
 510         ret = local_usbpll_enable(clk, 1);
 511         if (ret >= 0)
 512                 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
 513
 514         return ret;
 515 }
 516
 517 static struct clk clk_usbpll = {
 518         .parent         = &osc_main,
 519         .set_rate       = local_usbpll_set_rate,
 520         .enable         = local_usbpll_enable,
 521         .rate           = 48000, /* In KHz */
 522         .get_rate       = local_return_parent_rate,
 523         .round_rate     = local_usbpll_round_rate,
 524 };
 525
 526 static u32 clk_get_hclk_div(void)
 527 {
 528         static const u32 hclkdivs[4] = {1, 2, 4, 4};
 529         return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
 530                 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
 531 }
 532
 533 static struct clk clk_hclk = {
 534         .parent         = &clk_armpll,
 535         .get_rate       = local_return_parent_rate,
 536 };
 537
 538 static struct clk clk_pclk = {
 539         .parent         = &clk_armpll,
 540         .get_rate       = local_return_parent_rate,
 541 };
 542
 543 static int local_onoff_enable(struct clk *clk, int enable)
 544 {
 545         u32 tmp;
 546
 547         tmp = __raw_readl(clk->enable_reg);
 548
 549         if (enable == 0)
 550                 tmp &= ~clk->enable_mask;
 551         else
 552                 tmp |= clk->enable_mask;
 553
 554         __raw_writel(tmp, clk->enable_reg);
 555
 556         return 0;
 557 }
 558
 559 /* Peripheral clock sources */
 560 static struct clk clk_timer0 = {
 561         .parent         = &clk_pclk,
 562         .enable         = local_onoff_enable,
 563         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 564         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
 565         .get_rate       = local_return_parent_rate,
 566 };
 567 static struct clk clk_timer1 = {
 568         .parent         = &clk_pclk,
 569         .enable         = local_onoff_enable,
 570         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 571         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
 572         .get_rate       = local_return_parent_rate,
 573 };
 574 static struct clk clk_timer2 = {
 575         .parent         = &clk_pclk,
 576         .enable         = local_onoff_enable,
 577         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 578         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
 579         .get_rate       = local_return_parent_rate,
 580 };
 581 static struct clk clk_timer3 = {
 582         .parent         = &clk_pclk,
 583         .enable         = local_onoff_enable,
 584         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 585         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
 586         .get_rate       = local_return_parent_rate,
 587 };
 588 static struct clk clk_wdt = {
 589         .parent         = &clk_pclk,
 590         .enable         = local_onoff_enable,
 591         .enable_reg     = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
 592         .enable_mask    = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
 593         .get_rate       = local_return_parent_rate,
 594 };
 595 static struct clk clk_vfp9 = {
 596         .parent         = &clk_pclk,
 597         .enable         = local_onoff_enable,
 598         .enable_reg     = LPC32XX_CLKPWR_DEBUG_CTRL,
 599         .enable_mask    = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
 600         .get_rate       = local_return_parent_rate,
 601 };
 602 static struct clk clk_dma = {
 603         .parent         = &clk_hclk,
 604         .enable         = local_onoff_enable,
 605         .enable_reg     = LPC32XX_CLKPWR_DMA_CLK_CTRL,
 606         .enable_mask    = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
 607         .get_rate       = local_return_parent_rate,
 608 };
 609
 610 static struct clk clk_uart3 = {
 611         .parent         = &clk_pclk,
 612         .enable         = local_onoff_enable,
 613         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 614         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
 615         .get_rate       = local_return_parent_rate,
 616 };
 617
 618 static struct clk clk_uart4 = {
 619         .parent         = &clk_pclk,
 620         .enable         = local_onoff_enable,
 621         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 622         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
 623         .get_rate       = local_return_parent_rate,
 624 };
 625
 626 static struct clk clk_uart5 = {
 627         .parent         = &clk_pclk,
 628         .enable         = local_onoff_enable,
 629         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 630         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
 631         .get_rate       = local_return_parent_rate,
 632 };
 633
 634 static struct clk clk_uart6 = {
 635         .parent         = &clk_pclk,
 636         .enable         = local_onoff_enable,
 637         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 638         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
 639         .get_rate       = local_return_parent_rate,
 640 };
 641
 642 static struct clk clk_i2c0 = {
 643         .parent         = &clk_hclk,
 644         .enable         = local_onoff_enable,
 645         .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
 646         .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
 647         .get_rate       = local_return_parent_rate,
 648 };
 649
 650 static struct clk clk_i2c1 = {
 651         .parent         = &clk_hclk,
 652         .enable         = local_onoff_enable,
 653         .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
 654         .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
 655         .get_rate       = local_return_parent_rate,
 656 };
 657
 658 static struct clk clk_i2c2 = {
 659         .parent         = &clk_pclk,
 660         .enable         = local_onoff_enable,
 661         .enable_reg     = io_p2v(LPC32XX_USB_BASE + 0xFF4),
 662         .enable_mask    = 0x4,
 663         .get_rate       = local_return_parent_rate,
 664 };
 665
 666 static struct clk clk_ssp0 = {
 667         .parent         = &clk_hclk,
 668         .enable         = local_onoff_enable,
 669         .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
 670         .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
 671         .get_rate       = local_return_parent_rate,
 672 };
 673
 674 static struct clk clk_ssp1 = {
 675         .parent         = &clk_hclk,
 676         .enable         = local_onoff_enable,
 677         .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
 678         .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
 679         .get_rate       = local_return_parent_rate,
 680 };
 681
 682 static struct clk clk_kscan = {
 683         .parent         = &osc_32KHz,
 684         .enable         = local_onoff_enable,
 685         .enable_reg     = LPC32XX_CLKPWR_KEY_CLK_CTRL,
 686         .enable_mask    = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
 687         .get_rate       = local_return_parent_rate,
 688 };
 689
 690 static struct clk clk_nand = {
 691         .parent         = &clk_hclk,
 692         .enable         = local_onoff_enable,
 693         .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
 694         .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
 695         .get_rate       = local_return_parent_rate,
 696 };
 697
 698 static struct clk clk_i2s0 = {
 699         .parent         = &clk_hclk,
 700         .enable         = local_onoff_enable,
 701         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
 702         .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
 703         .get_rate       = local_return_parent_rate,
 704 };
 705
 706 static struct clk clk_i2s1 = {
 707         .parent         = &clk_hclk,
 708         .enable         = local_onoff_enable,
 709         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
 710         .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
 711         .get_rate       = local_return_parent_rate,
 712 };
 713
 714 static struct clk clk_net = {
 715         .parent         = &clk_hclk,
 716         .enable         = local_onoff_enable,
 717         .enable_reg     = LPC32XX_CLKPWR_MACCLK_CTRL,
 718         .enable_mask    = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
 719                 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
 720                 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
 721         .get_rate       = local_return_parent_rate,
 722 };
 723
 724 static struct clk clk_rtc = {
 725         .parent         = &osc_32KHz,
 726         .rate           = 1, /* 1 Hz */
 727         .get_rate       = local_return_parent_rate,
 728 };
 729
 730 static struct clk clk_usbd = {
 731         .parent         = &clk_usbpll,
 732         .enable         = local_onoff_enable,
 733         .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
 734         .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
 735         .get_rate       = local_return_parent_rate,
 736 };
 737
 738 static int tsc_onoff_enable(struct clk *clk, int enable)
 739 {
 740         u32 tmp;
 741
 742         /* Make sure 32KHz clock is the selected clock */
 743         tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 744         tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
 745         __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 746
 747         if (enable == 0)
 748                 __raw_writel(0, clk->enable_reg);
 749         else
 750                 __raw_writel(clk->enable_mask, clk->enable_reg);
 751
 752         return 0;
 753 }
 754
 755 static struct clk clk_tsc = {
 756         .parent         = &osc_32KHz,
 757         .enable         = tsc_onoff_enable,
 758         .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
 759         .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
 760         .get_rate       = local_return_parent_rate,
 761 };
 762
 763 static int mmc_onoff_enable(struct clk *clk, int enable)
 764 {
 765         u32 tmp;
 766
 767         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
 768                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
 769
 770         /* If rate is 0, disable clock */
 771         if (enable != 0)
 772                 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
 773
 774         /* Start clock at highest rate */
 775         if (!(tmp & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xF)))
 776                 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(1);
 777
 778         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 779
 780         return 0;
 781 }
 782
 783 static unsigned long mmc_get_rate(struct clk *clk)
 784 {
 785         u32 div, rate;
 786
 787         div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 788
 789         /* Get the parent clock rate */
 790         rate = clk->parent->get_rate(clk->parent);
 791
 792         /* Get the MMC controller clock divider value */
 793         div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
 794
 795         if (!div)
 796                 div = 1;
 797
 798         return rate / div;
 799 }
 800
 801 static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
 802 {
 803         unsigned long div, prate;
 804
 805         /* Get the parent clock rate */
 806         prate = clk->parent->get_rate(clk->parent);
 807
 808         if (rate >= prate)
 809                 return prate;
 810
 811         div = prate / rate;
 812         if (div > 0xf)
 813                 div = 0xf;
 814
 815         /*
 816          * The divider is forced to 1 to keep the SD clock granularity
 817          * good. Using a non-0 divider will limit the SD card clock rates
 818          * the SD driver can generate. Remove it if your feeling crazy.
 819          */
 820         div = 1;
 821
 822         return prate / div;
 823 }
 824
 825 static int mmc_set_rate(struct clk *clk, unsigned long rate)
 826 {
 827         u32 tmp;
 828         unsigned long prate, div, crate = mmc_round_rate(clk, rate);
 829
 830         prate = clk->parent->get_rate(clk->parent);
 831
 832         div = prate / crate;
 833
 834         /* The MMC clock must be on when accessing an MMC register */
 835         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
 836                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
 837         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
 838         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 839
 840         return 0;
 841 }
 842
 843 /*
 844  * This is the MMC IP clock, not the MMC CLK signal rate!
 845  */
 846 static struct clk clk_mmc = {
 847         .parent         = &clk_armpll,
 848         .set_rate       = mmc_set_rate,
 849         .get_rate       = mmc_get_rate,
 850         .round_rate     = mmc_round_rate,
 851         .enable         = mmc_onoff_enable,
 852         .enable_reg     = LPC32XX_CLKPWR_MS_CTRL,
 853         .enable_mask    = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 854 };
 855
 856 static unsigned long clcd_get_rate(struct clk *clk)
 857 {
 858         u32 tmp, div, rate, oldclk;
 859
 860         /* The LCD clock must be on when accessing an LCD register */
 861         oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 862         __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 863                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 864         tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
 865         __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
 866
 867         rate = clk->parent->get_rate(clk->parent);
 868
 869         /* Only supports internal clocking */
 870         if (tmp & TIM2_BCD)
 871                 return rate;
 872
 873         div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
 874         tmp = rate / (2 + div);
 875
 876         return tmp;
 877 }
 878
 879 static int clcd_set_rate(struct clk *clk, unsigned long rate)
 880 {
 881         u32 tmp, prate, div, oldclk;
 882
 883         /* The LCD clock must be on when accessing an LCD register */
 884         oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 885         __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 886                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 887
 888         tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
 889         prate = clk->parent->get_rate(clk->parent);
 890
 891         if (rate < prate) {
 892                 /* Find closest divider */
 893                 div = prate / rate;
 894                 if (div >= 2) {
 895                         div -= 2;
 896                         tmp &= ~TIM2_BCD;
 897                 }
 898
 899                 tmp &= ~(0xF800001F);
 900                 tmp |= (div & 0x1F);
 901                 tmp |= (((div >> 5) & 0x1F) << 27);
 902         }
 903
 904         __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
 905         __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
 906
 907         return 0;
 908 }
 909
 910 static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
 911 {
 912         u32 prate, div;
 913
 914         prate = clk->parent->get_rate(clk->parent);
 915
 916         if (rate >= prate)
 917                 rate = prate;
 918         else {
 919                 div = prate / rate;
 920                 if (div > 0x3ff)
 921                         div = 0x3ff;
 922
 923                 rate = prate / div;
 924         }
 925
 926         return rate;
 927 }
 928
 929 static struct clk clk_lcd = {
 930         .parent         = &clk_hclk,
 931         .set_rate       = clcd_set_rate,
 932         .get_rate       = clcd_get_rate,
 933         .round_rate     = clcd_round_rate,
 934         .enable         = local_onoff_enable,
 935         .enable_reg     = LPC32XX_CLKPWR_LCDCLK_CTRL,
 936         .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 937 };
 938
 939 static inline void clk_lock(void)
 940 {
 941         mutex_lock(&clkm_lock);
 942 }
 943
 944 static inline void clk_unlock(void)
 945 {
 946         mutex_unlock(&clkm_lock);
 947 }
 948
 949 static void local_clk_disable(struct clk *clk)
 950 {
 951         // WARN_ON(clk->usecount == 0);
 952
 953         /* Don't attempt to disable clock if it has no users */
 954         if (clk->usecount > 0) {
 955                 clk->usecount--;
 956
 957                 /* Only disable clock when it has no more users */
 958                 if ((clk->usecount == 0) && (clk->enable))
 959                         clk->enable(clk, 0);
 960
 961                 /* Check parent clocks, they may need to be disabled too */
 962                 if (clk->parent)
 963                         local_clk_disable(clk->parent);
 964         }
 965 }
 966
 967 static int local_clk_enable(struct clk *clk)
 968 {
 969         int ret = 0;
 970
 971         /* Enable parent clocks first and update use counts */
 972         if (clk->parent)
 973                 ret = local_clk_enable(clk->parent);
 974
 975         if (!ret) {
 976                 /* Only enable clock if it's currently disabled */
 977                 if ((clk->usecount == 0) && (clk->enable))
 978                         ret = clk->enable(clk, 1);
 979
 980                 if (!ret)
 981                         clk->usecount++;
 982                 else if (clk->parent)
 983                         local_clk_disable(clk->parent);
 984         }
 985
 986         return ret;
 987 }
 988
 989 /*
 990  * clk_enable - inform the system when the clock source should be running.
 991  */
 992 int clk_enable(struct clk *clk)
 993 {
 994         int ret;
 995
 996         clk_lock();
 997         ret = local_clk_enable(clk);
 998         clk_unlock();
 999
1000         return ret;
1001 }
1002 EXPORT_SYMBOL(clk_enable);
1003
1004 /*
1005  * clk_disable - inform the system when the clock source is no longer required
1006  */
1007 void clk_disable(struct clk *clk)
1008 {
1009         clk_lock();
1010         local_clk_disable(clk);
1011         clk_unlock();
1012 }
1013 EXPORT_SYMBOL(clk_disable);
1014
1015 /*
1016  * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
1017  */
1018 unsigned long clk_get_rate(struct clk *clk)
1019 {
1020         unsigned long rate;
1021
1022         clk_lock();
1023         rate = clk->get_rate(clk);
1024         clk_unlock();
1025
1026         return rate;
1027 }
1028 EXPORT_SYMBOL(clk_get_rate);
1029
1030 /*
1031  * clk_set_rate - set the clock rate for a clock source
1032  */
1033 int clk_set_rate(struct clk *clk, unsigned long rate)
1034 {
1035         int ret = -EINVAL;
1036
1037         /*
1038          * Most system clocks can only be enabled or disabled, with
1039          * the actual rate set as part of the peripheral dividers
1040          * instead of high level clock control
1041          */
1042         if (clk->set_rate) {
1043                 clk_lock();
1044                 ret = clk->set_rate(clk, rate);
1045                 clk_unlock();
1046         }
1047
1048         return ret;
1049 }
1050 EXPORT_SYMBOL(clk_set_rate);
1051
1052 /*
1053  * clk_round_rate - adjust a rate to the exact rate a clock can provide
1054  */
1055 long clk_round_rate(struct clk *clk, unsigned long rate)
1056 {
1057         clk_lock();
1058
1059         if (clk->round_rate)
1060                 rate = clk->round_rate(clk, rate);
1061         else
1062                 rate = clk->get_rate(clk);
1063
1064         clk_unlock();
1065
1066         return rate;
1067 }
1068 EXPORT_SYMBOL(clk_round_rate);
1069
1070 /*
1071  * clk_set_parent - set the parent clock source for this clock
1072  */
1073 int clk_set_parent(struct clk *clk, struct clk *parent)
1074 {
1075         /* Clock re-parenting is not supported */
1076         return -EINVAL;
1077 }
1078 EXPORT_SYMBOL(clk_set_parent);
1079
1080 /*
1081  * clk_get_parent - get the parent clock source for this clock
1082  */
1083 struct clk *clk_get_parent(struct clk *clk)
1084 {
1085         return clk->parent;
1086 }
1087 EXPORT_SYMBOL(clk_get_parent);
1088
1089 #define _REGISTER_CLOCK(d, n, c) \
1090         { \
1091                 .dev_id = (d), \
1092                 .con_id = (n), \
1093                 .clk = &(c), \
1094         },
1095
1096 static struct clk_lookup lookups[] = {
1097         _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
1098         _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
1099         _REGISTER_CLOCK(NULL, "osc_main", osc_main)
1100         _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
1101         _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
1102         _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
1103         _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
1104         _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
1105         _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
1106         _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
1107         _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
1108         _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
1109         _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
1110         _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
1111         _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
1112         _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
1113         _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
1114         _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
1115         _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
1116         _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
1117         _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
1118         _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
1119         _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
1120         _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
1121         _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
1122         _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1123         _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
1124         _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
1125         _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
1126         _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
1127         _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
1128         _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
1129         _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
1130         _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
1131 };
1132
1133 static int __init clk_init(void)
1134 {
1135         int i;
1136
1137         for (i = 0; i < ARRAY_SIZE(lookups); i++)
1138                 clkdev_add(&lookups[i]);
1139
1140         /*
1141          * Setup muxed SYSCLK for HCLK PLL base -this selects the
1142          * parent clock used for the ARM PLL and is used to derive
1143          * the many system clock rates in the device.
1144          */
1145         if (clk_is_sysclk_mainosc() != 0)
1146                 clk_sys.parent = &osc_main;
1147         else
1148                 clk_sys.parent = &osc_pll397;
1149
1150         clk_sys.rate = clk_sys.parent->rate;
1151
1152         /* Compute the current ARM PLL and USB PLL frequencies */
1153         local_update_armpll_rate();
1154
1155         /* Compute HCLK and PCLK bus rates */
1156         clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1157         clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1158
1159         /*
1160          * Enable system clocks - this step is somewhat formal, as the
1161          * clocks are already running, but it does get the clock data
1162          * inline with the actual system state. Never disable these
1163          * clocks as they will only stop if the system is going to sleep.
1164          * In that case, the chip/system power management functions will
1165          * handle clock gating.
1166          */
1167         if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1168                 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1169
1170         /*
1171          * Timers 0 and 1 were enabled and are being used by the high
1172          * resolution tick function prior to this driver being initialized.
1173          * Tag them now as used.
1174          */
1175         if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1176                 printk(KERN_ERR "Error enabling timer tick clocks\n");
1177
1178         return 0;
1179 }
1180 core_initcall(clk_init);
1181