arch/arm/mach-lpc32xx/clock.c

   1 /*
   2  * arch/arm/mach-lpc32xx/clock.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 /*
  20  * LPC32xx clock management driver overview
  21  *
  22  * The LPC32XX contains a number of high level system clocks that can be
  23  * generated from different sources. These system clocks are used to
  24  * generate the CPU and bus rates and the individual peripheral clocks in
  25  * the system. When Linux is started by the boot loader, the system
  26  * clocks are already running. Stopping a system clock during normal
  27  * Linux operation should never be attempted, as peripherals that require
  28  * those clocks will quit working (ie, DRAM).
  29  *
  30  * The LPC32xx high level clock tree looks as follows. Clocks marked with
  31  * an asterisk are always on and cannot be disabled. Clocks marked with
  32  * an ampersand can only be disabled in CPU suspend mode. Clocks marked
  33  * with a caret are always on if it is the selected clock for the SYSCLK
  34  * source. The clock that isn't used for SYSCLK can be enabled and
  35  * disabled normally.
  36  *                               32KHz oscillator*
  37  *                               /      |      \
  38  *                             RTC*   PLL397^ TOUCH
  39  *                                     /
  40  *               Main oscillator^     /
  41  *                   |        \      /
  42  *                   |         SYSCLK&
  43  *                   |            \
  44  *                   |             \
  45  *                USB_PLL       HCLK_PLL&
  46  *                   |           |    |
  47  *            USB host/device  PCLK&  |
  48  *                               |    |
  49  *                             Peripherals
  50  *
  51  * The CPU and chip bus rates are derived from the HCLK PLL, which can
  52  * generate various clock rates up to 266MHz and beyond. The internal bus
  53  * rates (PCLK and HCLK) are generated from dividers based on the HCLK
  54  * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
  55  * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
  56  * level clocks are based on either HCLK or PCLK, but have their own
  57  * dividers as part of the IP itself. Because of this, the system clock
  58  * rates should not be changed.
  59  *
  60  * The HCLK PLL is clocked from SYSCLK, which can be derived from the
  61  * main oscillator or PLL397. PLL397 generates a rate that is 397 times
  62  * the 32KHz oscillator rate. The main oscillator runs at the selected
  63  * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
  64  * is normally 13MHz, but depends on the selection of external crystals
  65  * or oscillators. If USB operation is required, the main oscillator must
  66  * be used in the system.
  67  *
  68  * Switching SYSCLK between sources during normal Linux operation is not
  69  * supported. SYSCLK is preset in the bootloader. Because of the
  70  * complexities of clock management during clock frequency changes,
  71  * there are some limitations to the clock driver explained below:
  72  * - The PLL397 and main oscillator can be enabled and disabled by the
  73  *   clk_enable() and clk_disable() functions unless SYSCLK is based
  74  *   on that clock. This allows the other oscillator that isn't driving
  75  *   the HCLK PLL to be used as another system clock that can be routed
  76  *   to an external pin.
  77  * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
  78  *   this driver.
  79  * - HCLK and PCLK rates cannot be changed as part of this driver.
  80  * - Most peripherals have their own dividers are part of the peripheral
  81  *   block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
  82  *   will also impact the individual peripheral rates.
  83  */
  84
  85 #include <linux/kernel.h>
  86 #include <linux/list.h>
  87 #include <linux/errno.h>
  88 #include <linux/device.h>
  89 #include <linux/delay.h>
  90 #include <linux/err.h>
  91 #include <linux/clk.h>
  92 #include <linux/amba/bus.h>
  93 #include <linux/amba/clcd.h>
  94
  95 #include <mach/hardware.h>
  96 #include <asm/clkdev.h>
  97 #include <mach/clkdev.h>
  98 #include <mach/platform.h>
  99 #include "clock.h"
 100 #include "common.h"
 101
 102 static int usb_pll_enable, usb_pll_valid;
 103
 104 static struct clk clk_armpll;
 105 static struct clk clk_usbpll;
 106 static DEFINE_MUTEX(clkm_lock);
 107
 108 /*
 109  * Post divider values for PLLs based on selected register value
 110  */
 111 static const u32 pll_postdivs[4] = {1, 2, 4, 8};
 112
 113 static unsigned long local_return_parent_rate(struct clk *clk)
 114 {
 115         /*
 116          * If a clock has a rate of 0, then it inherits it's parent
 117          * clock rate
 118          */
 119         while (clk->rate == 0)
 120                 clk = clk->parent;
 121
 122         return clk->rate;
 123 }
 124
 125 /* 32KHz clock has a fixed rate and is not stoppable */
 126 static struct clk osc_32KHz = {
 127         .rate           = LPC32XX_CLOCK_OSC_FREQ,
 128         .get_rate       = local_return_parent_rate,
 129 };
 130
 131 static int local_pll397_enable(struct clk *clk, int enable)
 132 {
 133         u32 reg;
 134         unsigned long timeout = jiffies + msecs_to_jiffies(10);
 135
 136         reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
 137
 138         if (enable == 0) {
 139                 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
 140                 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
 141         } else {
 142                 /* Enable PLL397 */
 143                 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
 144                 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
 145
 146                 /* Wait for PLL397 lock */
 147                 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
 148                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
 149                         (timeout > jiffies))
 150                         cpu_relax();
 151
 152                 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
 153                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
 154                         return -ENODEV;
 155         }
 156
 157         return 0;
 158 }
 159
 160 static int local_oscmain_enable(struct clk *clk, int enable)
 161 {
 162         u32 reg;
 163         unsigned long timeout = jiffies + msecs_to_jiffies(10);
 164
 165         reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 166
 167         if (enable == 0) {
 168                 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
 169                 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 170         } else {
 171                 /* Enable main oscillator */
 172                 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
 173                 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 174
 175                 /* Wait for main oscillator to start */
 176                 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
 177                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
 178                         (timeout > jiffies))
 179                         cpu_relax();
 180
 181                 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
 182                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
 183                         return -ENODEV;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static struct clk osc_pll397 = {
 190         .parent         = &osc_32KHz,
 191         .enable         = local_pll397_enable,
 192         .rate           = LPC32XX_CLOCK_OSC_FREQ * 397,
 193         .get_rate       = local_return_parent_rate,
 194 };
 195
 196 static struct clk osc_main = {
 197         .enable         = local_oscmain_enable,
 198         .rate           = LPC32XX_MAIN_OSC_FREQ,
 199         .get_rate       = local_return_parent_rate,
 200 };
 201
 202 static struct clk clk_sys;
 203
 204 /*
 205  * Convert a PLL register value to a PLL output frequency
 206  */
 207 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
 208 {
 209         struct clk_pll_setup pllcfg;
 210
 211         pllcfg.cco_bypass_b15 = 0;
 212         pllcfg.direct_output_b14 = 0;
 213         pllcfg.fdbk_div_ctrl_b13 = 0;
 214         if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
 215                 pllcfg.cco_bypass_b15 = 1;
 216         if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
 217                 pllcfg.direct_output_b14 = 1;
 218         if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
 219                 pllcfg.fdbk_div_ctrl_b13 = 1;
 220         pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
 221         pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
 222         pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
 223
 224         return clk_check_pll_setup(inputclk, &pllcfg);
 225 }
 226
 227 /*
 228  * Setup the HCLK PLL with a PLL structure
 229  */
 230 static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
 231 {
 232         u32 tv, tmp = 0;
 233
 234         if (PllSetup->analog_on != 0)
 235                 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
 236         if (PllSetup->cco_bypass_b15 != 0)
 237                 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
 238         if (PllSetup->direct_output_b14 != 0)
 239                 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
 240         if (PllSetup->fdbk_div_ctrl_b13 != 0)
 241                 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
 242
 243         tv = ffs(PllSetup->pll_p) - 1;
 244         if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
 245                 return 0;
 246
 247         tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
 248         tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
 249         tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
 250
 251         return tmp;
 252 }
 253
 254 /*
 255  * Update the ARM core PLL frequency rate variable from the actual PLL setting
 256  */
 257 static void local_update_armpll_rate(void)
 258 {
 259         u32 clkin, pllreg;
 260
 261         clkin = clk_armpll.parent->rate;
 262         pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
 263
 264         clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
 265 }
 266
 267 /*
 268  * Find a PLL configuration for the selected input frequency
 269  */
 270 static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
 271         struct clk_pll_setup *pllsetup)
 272 {
 273         u32 ifreq, freqtol, m, n, p, fclkout;
 274
 275         /* Determine frequency tolerance limits */
 276         freqtol = target_freq / 250;
 277         ifreq = pllin_freq;
 278
 279         /* Is direct bypass mode possible? */
 280         if (abs(pllin_freq - target_freq) <= freqtol) {
 281                 pllsetup->analog_on = 0;
 282                 pllsetup->cco_bypass_b15 = 1;
 283                 pllsetup->direct_output_b14 = 1;
 284                 pllsetup->fdbk_div_ctrl_b13 = 1;
 285                 pllsetup->pll_p = pll_postdivs[0];
 286                 pllsetup->pll_n = 1;
 287                 pllsetup->pll_m = 1;
 288                 return clk_check_pll_setup(ifreq, pllsetup);
 289         } else if (target_freq <= ifreq) {
 290                 pllsetup->analog_on = 0;
 291                 pllsetup->cco_bypass_b15 = 1;
 292                 pllsetup->direct_output_b14 = 0;
 293                 pllsetup->fdbk_div_ctrl_b13 = 1;
 294                 pllsetup->pll_n = 1;
 295                 pllsetup->pll_m = 1;
 296                 for (p = 0; p <= 3; p++) {
 297                         pllsetup->pll_p = pll_postdivs[p];
 298                         fclkout = clk_check_pll_setup(ifreq, pllsetup);
 299                         if (abs(target_freq - fclkout) <= freqtol)
 300                                 return fclkout;
 301                 }
 302         }
 303
 304         /* Is direct mode possible? */
 305         pllsetup->analog_on = 1;
 306         pllsetup->cco_bypass_b15 = 0;
 307         pllsetup->direct_output_b14 = 1;
 308         pllsetup->fdbk_div_ctrl_b13 = 0;
 309         pllsetup->pll_p = pll_postdivs[0];
 310         for (m = 1; m <= 256; m++) {
 311                 for (n = 1; n <= 4; n++) {
 312                         /* Compute output frequency for this value */
 313                         pllsetup->pll_n = n;
 314                         pllsetup->pll_m = m;
 315                         fclkout = clk_check_pll_setup(ifreq,
 316                                 pllsetup);
 317                         if (abs(target_freq - fclkout) <=
 318                                 freqtol)
 319                                 return fclkout;
 320                 }
 321         }
 322
 323         /* Is integer mode possible? */
 324         pllsetup->analog_on = 1;
 325         pllsetup->cco_bypass_b15 = 0;
 326         pllsetup->direct_output_b14 = 0;
 327         pllsetup->fdbk_div_ctrl_b13 = 1;
 328         for (m = 1; m <= 256; m++) {
 329                 for (n = 1; n <= 4; n++) {
 330                         for (p = 0; p < 4; p++) {
 331                                 /* Compute output frequency */
 332                                 pllsetup->pll_p = pll_postdivs[p];
 333                                 pllsetup->pll_n = n;
 334                                 pllsetup->pll_m = m;
 335                                 fclkout = clk_check_pll_setup(
 336                                         ifreq, pllsetup);
 337                                 if (abs(target_freq - fclkout) <= freqtol)
 338                                         return fclkout;
 339                         }
 340                 }
 341         }
 342
 343         /* Try non-integer mode */
 344         pllsetup->analog_on = 1;
 345         pllsetup->cco_bypass_b15 = 0;
 346         pllsetup->direct_output_b14 = 0;
 347         pllsetup->fdbk_div_ctrl_b13 = 0;
 348         for (m = 1; m <= 256; m++) {
 349                 for (n = 1; n <= 4; n++) {
 350                         for (p = 0; p < 4; p++) {
 351                                 /* Compute output frequency */
 352                                 pllsetup->pll_p = pll_postdivs[p];
 353                                 pllsetup->pll_n = n;
 354                                 pllsetup->pll_m = m;
 355                                 fclkout = clk_check_pll_setup(
 356                                         ifreq, pllsetup);
 357                                 if (abs(target_freq - fclkout) <= freqtol)
 358                                         return fclkout;
 359                         }
 360                 }
 361         }
 362
 363         return 0;
 364 }
 365
 366 static struct clk clk_armpll = {
 367         .parent         = &clk_sys,
 368         .get_rate       = local_return_parent_rate,
 369 };
 370
 371 /*
 372  * Setup the USB PLL with a PLL structure
 373  */
 374 static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
 375 {
 376         u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
 377
 378         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
 379         reg |= tmp;
 380         __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 381
 382         return clk_check_pll_setup(clk_usbpll.parent->rate,
 383                 pHCLKPllSetup);
 384 }
 385
 386 static int local_usbpll_enable(struct clk *clk, int enable)
 387 {
 388         u32 reg;
 389         int ret = 0;
 390         unsigned long timeout = jiffies + msecs_to_jiffies(20);
 391
 392         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 393
 394         __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
 395                 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
 396                 LPC32XX_CLKPWR_USB_CTRL);
 397         __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
 398                 LPC32XX_CLKPWR_USB_CTRL);
 399
 400         if (enable && usb_pll_valid && usb_pll_enable) {
 401                 ret = -ENODEV;
 402                 /*
 403                  * If the PLL rate has been previously set, then the rate
 404                  * in the PLL register is valid and can be enabled here.
 405                  * Otherwise, it needs to be enabled as part of setrate.
 406                  */
 407
 408                 /*
 409                  * Gate clock into PLL
 410                  */
 411                 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
 412                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 413
 414                 /*
 415                  * Enable PLL
 416                  */
 417                 reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
 418                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 419
 420                 /*
 421                  * Wait for PLL to lock
 422                  */
 423                 while ((timeout > jiffies) && (ret == -ENODEV)) {
 424                         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 425                         if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
 426                                 ret = 0;
 427                         else
 428                                 udelay(10);
 429                 }
 430
 431                 /*
 432                  * Gate clock from PLL if PLL is locked
 433                  */
 434                 if (ret == 0)
 435                         __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
 436                                 LPC32XX_CLKPWR_USB_CTRL);
 437                 else
 438                         __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
 439                                 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
 440                                 LPC32XX_CLKPWR_USB_CTRL);
 441         }
 442
 443         return ret;
 444 }
 445
 446 static unsigned long local_usbpll_round_rate(struct clk *clk,
 447         unsigned long rate)
 448 {
 449         u32 clkin, usbdiv;
 450         struct clk_pll_setup pllsetup;
 451
 452         /*
 453          * Unlike other clocks, this clock has a KHz input rate, so bump
 454          * it up to work with the PLL function
 455          */
 456         rate = rate * 1000;
 457
 458         clkin = clk->get_rate(clk);
 459         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 460                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 461         clkin = clkin / usbdiv;
 462
 463         /* Try to find a good rate setup */
 464         if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 465                 return 0;
 466
 467         return clk_check_pll_setup(clkin, &pllsetup);
 468 }
 469
 470 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
 471 {
 472         int ret = -ENODEV;
 473         u32 clkin, usbdiv;
 474         struct clk_pll_setup pllsetup;
 475
 476         /*
 477          * Unlike other clocks, this clock has a KHz input rate, so bump
 478          * it up to work with the PLL function
 479          */
 480         rate = rate * 1000;
 481
 482         clkin = clk->get_rate(clk->parent);
 483         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 484                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 485         clkin = clkin / usbdiv;
 486
 487         /* Try to find a good rate setup */
 488         if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 489                 return -EINVAL;
 490
 491         usb_pll_valid = 1;
 492         usb_pll_enable = 1;
 493
 494         /*
 495          * Disable PLL clocks during PLL change
 496          */
 497         local_usbpll_enable(clk, 0);
 498         pllsetup.analog_on = 0;
 499         local_clk_usbpll_setup(&pllsetup);
 500
 501         /*
 502          * Start USB PLL and check PLL status
 503          */
 504         usb_pll_enable = 1;
 505         ret = local_usbpll_enable(clk, 1);
 506         if (ret >= 0)
 507                 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
 508
 509         return ret;
 510 }
 511
 512 static struct clk clk_usbpll = {
 513         .parent         = &osc_main,
 514         .set_rate       = local_usbpll_set_rate,
 515         .enable         = local_usbpll_enable,
 516         .rate           = 48000, /* In KHz */
 517         .get_rate       = local_return_parent_rate,
 518         .round_rate     = local_usbpll_round_rate,
 519 };
 520
 521 static u32 clk_get_hclk_div(void)
 522 {
 523         static const u32 hclkdivs[4] = {1, 2, 4, 4};
 524         return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
 525                 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
 526 }
 527
 528 static struct clk clk_hclk = {
 529         .parent         = &clk_armpll,
 530         .get_rate       = local_return_parent_rate,
 531 };
 532
 533 static struct clk clk_pclk = {
 534         .parent         = &clk_armpll,
 535         .get_rate       = local_return_parent_rate,
 536 };
 537
 538 static int local_onoff_enable(struct clk *clk, int enable)
 539 {
 540         u32 tmp;
 541
 542         tmp = __raw_readl(clk->enable_reg);
 543
 544         if (enable == 0)
 545                 tmp &= ~clk->enable_mask;
 546         else
 547                 tmp |= clk->enable_mask;
 548
 549         __raw_writel(tmp, clk->enable_reg);
 550
 551         return 0;
 552 }
 553
 554 /* Peripheral clock sources */
 555 static struct clk clk_timer0 = {
 556         .parent         = &clk_pclk,
 557         .enable         = local_onoff_enable,
 558         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 559         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
 560         .get_rate       = local_return_parent_rate,
 561 };
 562 static struct clk clk_timer1 = {
 563         .parent         = &clk_pclk,
 564         .enable         = local_onoff_enable,
 565         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 566         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
 567         .get_rate       = local_return_parent_rate,
 568 };
 569 static struct clk clk_timer2 = {
 570         .parent         = &clk_pclk,
 571         .enable         = local_onoff_enable,
 572         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 573         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
 574         .get_rate       = local_return_parent_rate,
 575 };
 576 static struct clk clk_timer3 = {
 577         .parent         = &clk_pclk,
 578         .enable         = local_onoff_enable,
 579         .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
 580         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
 581         .get_rate       = local_return_parent_rate,
 582 };
 583 static struct clk clk_wdt = {
 584         .parent         = &clk_pclk,
 585         .enable         = local_onoff_enable,
 586         .enable_reg     = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
 587         .enable_mask    = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
 588         .get_rate       = local_return_parent_rate,
 589 };
 590 static struct clk clk_vfp9 = {
 591         .parent         = &clk_pclk,
 592         .enable         = local_onoff_enable,
 593         .enable_reg     = LPC32XX_CLKPWR_DEBUG_CTRL,
 594         .enable_mask    = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
 595         .get_rate       = local_return_parent_rate,
 596 };
 597 static struct clk clk_dma = {
 598         .parent         = &clk_hclk,
 599         .enable         = local_onoff_enable,
 600         .enable_reg     = LPC32XX_CLKPWR_DMA_CLK_CTRL,
 601         .enable_mask    = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
 602         .get_rate       = local_return_parent_rate,
 603 };
 604
 605 static struct clk clk_uart3 = {
 606         .parent         = &clk_pclk,
 607         .enable         = local_onoff_enable,
 608         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 609         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
 610         .get_rate       = local_return_parent_rate,
 611 };
 612
 613 static struct clk clk_uart4 = {
 614         .parent         = &clk_pclk,
 615         .enable         = local_onoff_enable,
 616         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 617         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
 618         .get_rate       = local_return_parent_rate,
 619 };
 620
 621 static struct clk clk_uart5 = {
 622         .parent         = &clk_pclk,
 623         .enable         = local_onoff_enable,
 624         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 625         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
 626         .get_rate       = local_return_parent_rate,
 627 };
 628
 629 static struct clk clk_uart6 = {
 630         .parent         = &clk_pclk,
 631         .enable         = local_onoff_enable,
 632         .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
 633         .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
 634         .get_rate       = local_return_parent_rate,
 635 };
 636
 637 static struct clk clk_i2c0 = {
 638         .parent         = &clk_hclk,
 639         .enable         = local_onoff_enable,
 640         .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
 641         .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
 642         .get_rate       = local_return_parent_rate,
 643 };
 644
 645 static struct clk clk_i2c1 = {
 646         .parent         = &clk_hclk,
 647         .enable         = local_onoff_enable,
 648         .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
 649         .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
 650         .get_rate       = local_return_parent_rate,
 651 };
 652
 653 static struct clk clk_i2c2 = {
 654         .parent         = &clk_pclk,
 655         .enable         = local_onoff_enable,
 656         .enable_reg     = io_p2v(LPC32XX_USB_BASE + 0xFF4),
 657         .enable_mask    = 0x4,
 658         .get_rate       = local_return_parent_rate,
 659 };
 660
 661 static struct clk clk_ssp0 = {
 662         .parent         = &clk_hclk,
 663         .enable         = local_onoff_enable,
 664         .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
 665         .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
 666         .get_rate       = local_return_parent_rate,
 667 };
 668
 669 static struct clk clk_ssp1 = {
 670         .parent         = &clk_hclk,
 671         .enable         = local_onoff_enable,
 672         .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
 673         .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
 674         .get_rate       = local_return_parent_rate,
 675 };
 676
 677 static struct clk clk_kscan = {
 678         .parent         = &osc_32KHz,
 679         .enable         = local_onoff_enable,
 680         .enable_reg     = LPC32XX_CLKPWR_KEY_CLK_CTRL,
 681         .enable_mask    = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
 682         .get_rate       = local_return_parent_rate,
 683 };
 684
 685 static struct clk clk_nand = {
 686         .parent         = &clk_hclk,
 687         .enable         = local_onoff_enable,
 688         .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
 689         .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
 690         .get_rate       = local_return_parent_rate,
 691 };
 692
 693 static struct clk clk_i2s0 = {
 694         .parent         = &clk_hclk,
 695         .enable         = local_onoff_enable,
 696         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
 697         .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
 698         .get_rate       = local_return_parent_rate,
 699 };
 700
 701 static struct clk clk_i2s1 = {
 702         .parent         = &clk_hclk,
 703         .enable         = local_onoff_enable,
 704         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
 705         .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
 706         .get_rate       = local_return_parent_rate,
 707 };
 708
 709 static struct clk clk_net = {
 710         .parent         = &clk_hclk,
 711         .enable         = local_onoff_enable,
 712         .enable_reg     = LPC32XX_CLKPWR_MACCLK_CTRL,
 713         .enable_mask    = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
 714                 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
 715                 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
 716         .get_rate       = local_return_parent_rate,
 717 };
 718
 719 static struct clk clk_rtc = {
 720         .parent         = &osc_32KHz,
 721         .rate           = 1, /* 1 Hz */
 722         .get_rate       = local_return_parent_rate,
 723 };
 724
 725 static struct clk clk_usbd = {
 726         .parent         = &clk_usbpll,
 727         .enable         = local_onoff_enable,
 728         .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
 729         .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
 730         .get_rate       = local_return_parent_rate,
 731 };
 732
 733 static int tsc_onoff_enable(struct clk *clk, int enable)
 734 {
 735         u32 tmp;
 736
 737         /* Make sure 32KHz clock is the selected clock */
 738         tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 739         tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
 740         __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
 741
 742         if (enable == 0)
 743                 __raw_writel(0, clk->enable_reg);
 744         else
 745                 __raw_writel(clk->enable_mask, clk->enable_reg);
 746
 747         return 0;
 748 }
 749
 750 static struct clk clk_tsc = {
 751         .parent         = &osc_32KHz,
 752         .enable         = tsc_onoff_enable,
 753         .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
 754         .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
 755         .get_rate       = local_return_parent_rate,
 756 };
 757
 758 static int mmc_onoff_enable(struct clk *clk, int enable)
 759 {
 760         u32 tmp;
 761
 762         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
 763                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
 764
 765         /* If rate is 0, disable clock */
 766         if (enable != 0)
 767                 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
 768
 769         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 770
 771         return 0;
 772 }
 773
 774 static unsigned long mmc_get_rate(struct clk *clk)
 775 {
 776         u32 div, rate, oldclk;
 777
 778         /* The MMC clock must be on when accessing an MMC register */
 779         oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 780         __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 781                 LPC32XX_CLKPWR_MS_CTRL);
 782         div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 783         __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
 784
 785         /* Get the parent clock rate */
 786         rate = clk->parent->get_rate(clk->parent);
 787
 788         /* Get the MMC controller clock divider value */
 789         div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
 790
 791         if (!div)
 792                 div = 1;
 793
 794         return rate / div;
 795 }
 796
 797 static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
 798 {
 799         unsigned long div, prate;
 800
 801         /* Get the parent clock rate */
 802         prate = clk->parent->get_rate(clk->parent);
 803
 804         if (rate >= prate)
 805                 return prate;
 806
 807         div = prate / rate;
 808         if (div > 0xf)
 809                 div = 0xf;
 810
 811         return prate / div;
 812 }
 813
 814 static int mmc_set_rate(struct clk *clk, unsigned long rate)
 815 {
 816         u32 oldclk, tmp;
 817         unsigned long prate, div, crate = mmc_round_rate(clk, rate);
 818
 819         prate = clk->parent->get_rate(clk->parent);
 820
 821         div = prate / crate;
 822
 823         /* The MMC clock must be on when accessing an MMC register */
 824         oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 825         __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 826                 LPC32XX_CLKPWR_MS_CTRL);
 827         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
 828                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
 829         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
 830         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 831
 832         __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
 833
 834         return 0;
 835 }
 836
 837 static struct clk clk_mmc = {
 838         .parent         = &clk_armpll,
 839         .set_rate       = mmc_set_rate,
 840         .get_rate       = mmc_get_rate,
 841         .round_rate     = mmc_round_rate,
 842         .enable         = mmc_onoff_enable,
 843         .enable_reg     = LPC32XX_CLKPWR_MS_CTRL,
 844         .enable_mask    = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 845 };
 846
 847 static unsigned long clcd_get_rate(struct clk *clk)
 848 {
 849         u32 tmp, div, rate, oldclk;
 850
 851         /* The LCD clock must be on when accessing an LCD register */
 852         oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 853         __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 854                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 855         tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
 856         __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
 857
 858         rate = clk->parent->get_rate(clk->parent);
 859
 860         /* Only supports internal clocking */
 861         if (tmp & TIM2_BCD)
 862                 return rate;
 863
 864         div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
 865         tmp = rate / (2 + div);
 866
 867         return tmp;
 868 }
 869
 870 static int clcd_set_rate(struct clk *clk, unsigned long rate)
 871 {
 872         u32 tmp, prate, div, oldclk;
 873
 874         /* The LCD clock must be on when accessing an LCD register */
 875         oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 876         __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 877                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 878
 879         tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
 880         prate = clk->parent->get_rate(clk->parent);
 881
 882         if (rate < prate) {
 883                 /* Find closest divider */
 884                 div = prate / rate;
 885                 if (div >= 2) {
 886                         div -= 2;
 887                         tmp &= ~TIM2_BCD;
 888                 }
 889
 890                 tmp &= ~(0xF800001F);
 891                 tmp |= (div & 0x1F);
 892                 tmp |= (((div >> 5) & 0x1F) << 27);
 893         }
 894
 895         __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
 896         __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
 897
 898         return 0;
 899 }
 900
 901 static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
 902 {
 903         u32 prate, div;
 904
 905         prate = clk->parent->get_rate(clk->parent);
 906
 907         if (rate >= prate)
 908                 rate = prate;
 909         else {
 910                 div = prate / rate;
 911                 if (div > 0x3ff)
 912                         div = 0x3ff;
 913
 914                 rate = prate / div;
 915         }
 916
 917         return rate;
 918 }
 919
 920 static struct clk clk_lcd = {
 921         .parent         = &clk_hclk,
 922         .set_rate       = clcd_set_rate,
 923         .get_rate       = clcd_get_rate,
 924         .round_rate     = clcd_round_rate,
 925         .enable         = local_onoff_enable,
 926         .enable_reg     = LPC32XX_CLKPWR_LCDCLK_CTRL,
 927         .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 928 };
 929
 930 static inline void clk_lock(void)
 931 {
 932         mutex_lock(&clkm_lock);
 933 }
 934
 935 static inline void clk_unlock(void)
 936 {
 937         mutex_unlock(&clkm_lock);
 938 }
 939
 940 static void local_clk_disable(struct clk *clk)
 941 {
 942         // WARN_ON(clk->usecount == 0);
 943
 944         /* Don't attempt to disable clock if it has no users */
 945         if (clk->usecount > 0) {
 946                 clk->usecount--;
 947
 948                 /* Only disable clock when it has no more users */
 949                 if ((clk->usecount == 0) && (clk->enable))
 950                         clk->enable(clk, 0);
 951
 952                 /* Check parent clocks, they may need to be disabled too */
 953                 if (clk->parent)
 954                         local_clk_disable(clk->parent);
 955         }
 956 }
 957
 958 static int local_clk_enable(struct clk *clk)
 959 {
 960         int ret = 0;
 961
 962         /* Enable parent clocks first and update use counts */
 963         if (clk->parent)
 964                 ret = local_clk_enable(clk->parent);
 965
 966         if (!ret) {
 967                 /* Only enable clock if it's currently disabled */
 968                 if ((clk->usecount == 0) && (clk->enable))
 969                         ret = clk->enable(clk, 1);
 970
 971                 if (!ret)
 972                         clk->usecount++;
 973                 else if (clk->parent)
 974                         local_clk_disable(clk->parent);
 975         }
 976
 977         return ret;
 978 }
 979
 980 /*
 981  * clk_enable - inform the system when the clock source should be running.
 982  */
 983 int clk_enable(struct clk *clk)
 984 {
 985         int ret;
 986
 987         clk_lock();
 988         ret = local_clk_enable(clk);
 989         clk_unlock();
 990
 991         return ret;
 992 }
 993 EXPORT_SYMBOL(clk_enable);
 994
 995 /*
 996  * clk_disable - inform the system when the clock source is no longer required
 997  */
 998 void clk_disable(struct clk *clk)
 999 {
1000         clk_lock();
1001         local_clk_disable(clk);
1002         clk_unlock();
1003 }
1004 EXPORT_SYMBOL(clk_disable);
1005
1006 /*
1007  * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
1008  */
1009 unsigned long clk_get_rate(struct clk *clk)
1010 {
1011         unsigned long rate;
1012
1013         clk_lock();
1014         rate = clk->get_rate(clk);
1015         clk_unlock();
1016
1017         return rate;
1018 }
1019 EXPORT_SYMBOL(clk_get_rate);
1020
1021 /*
1022  * clk_set_rate - set the clock rate for a clock source
1023  */
1024 int clk_set_rate(struct clk *clk, unsigned long rate)
1025 {
1026         int ret = -EINVAL;
1027
1028         /*
1029          * Most system clocks can only be enabled or disabled, with
1030          * the actual rate set as part of the peripheral dividers
1031          * instead of high level clock control
1032          */
1033         if (clk->set_rate) {
1034                 clk_lock();
1035                 ret = clk->set_rate(clk, rate);
1036                 clk_unlock();
1037         }
1038
1039         return ret;
1040 }
1041 EXPORT_SYMBOL(clk_set_rate);
1042
1043 /*
1044  * clk_round_rate - adjust a rate to the exact rate a clock can provide
1045  */
1046 long clk_round_rate(struct clk *clk, unsigned long rate)
1047 {
1048         clk_lock();
1049
1050         if (clk->round_rate)
1051                 rate = clk->round_rate(clk, rate);
1052         else
1053                 rate = clk->get_rate(clk);
1054
1055         clk_unlock();
1056
1057         return rate;
1058 }
1059 EXPORT_SYMBOL(clk_round_rate);
1060
1061 /*
1062  * clk_set_parent - set the parent clock source for this clock
1063  */
1064 int clk_set_parent(struct clk *clk, struct clk *parent)
1065 {
1066         /* Clock re-parenting is not supported */
1067         return -EINVAL;
1068 }
1069 EXPORT_SYMBOL(clk_set_parent);
1070
1071 /*
1072  * clk_get_parent - get the parent clock source for this clock
1073  */
1074 struct clk *clk_get_parent(struct clk *clk)
1075 {
1076         return clk->parent;
1077 }
1078 EXPORT_SYMBOL(clk_get_parent);
1079
1080 #define _REGISTER_CLOCK(d, n, c) \
1081         { \
1082                 .dev_id = (d), \
1083                 .con_id = (n), \
1084                 .clk = &(c), \
1085         },
1086
1087 static struct clk_lookup lookups[] = {
1088         _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
1089         _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
1090         _REGISTER_CLOCK(NULL, "osc_main", osc_main)
1091         _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
1092         _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
1093         _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
1094         _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
1095         _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
1096         _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
1097         _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
1098         _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
1099         _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
1100         _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
1101         _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
1102         _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
1103         _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
1104         _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
1105         _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
1106         _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
1107         _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
1108         _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
1109         _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
1110         _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
1111         _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
1112         _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
1113         _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1114         _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
1115         _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
1116         _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
1117         _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
1118         _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
1119         _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
1120         _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
1121         _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
1122 };
1123
1124 static int __init clk_init(void)
1125 {
1126         int i;
1127
1128         for (i = 0; i < ARRAY_SIZE(lookups); i++)
1129                 clkdev_add(&lookups[i]);
1130
1131         /*
1132          * Setup muxed SYSCLK for HCLK PLL base -this selects the
1133          * parent clock used for the ARM PLL and is used to derive
1134          * the many system clock rates in the device.
1135          */
1136         if (clk_is_sysclk_mainosc() != 0)
1137                 clk_sys.parent = &osc_main;
1138         else
1139                 clk_sys.parent = &osc_pll397;
1140
1141         clk_sys.rate = clk_sys.parent->rate;
1142
1143         /* Compute the current ARM PLL and USB PLL frequencies */
1144         local_update_armpll_rate();
1145
1146         /* Compute HCLK and PCLK bus rates */
1147         clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1148         clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1149
1150         /*
1151          * Enable system clocks - this step is somewhat formal, as the
1152          * clocks are already running, but it does get the clock data
1153          * inline with the actual system state. Never disable these
1154          * clocks as they will only stop if the system is going to sleep.
1155          * In that case, the chip/system power management functions will
1156          * handle clock gating.
1157          */
1158         if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1159                 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1160
1161         /*
1162          * Timers 0 and 1 were enabled and are being used by the high
1163          * resolution tick function prior to this driver being initialized.
1164          * Tag them now as used.
1165          */
1166         if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1167                 printk(KERN_ERR "Error enabling timer tick clocks\n");
1168
1169         return 0;
1170 }
1171 core_initcall(clk_init);
1172